Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: 07 April 2020 01:00 To: Pragnesh Patel pragnesh.patel@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Atish Patra atish.patra@wdc.com; palmerdabbelt@google.com; Bin Meng bmeng.cn@gmail.com; Paul Walmsley paul.walmsley@sifive.com; Troy Benjegerdes troy.benjegerdes@sifive.com; Anup Patel anup.patel@wdc.com; Sagar Kadam sagar.kadam@sifive.com; Rick Chen rick@andestech.com Subject: Re: [PATCH v6 07/17] sifive: dts: fu540: Add DDR controller and phy register settings
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On Sun, Mar 29, 2020 at 10:36 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:
Add DDR controller and phy register settings, taken from fsbl (https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com
arch/riscv/dts/fu540-c000-u-boot.dtsi | 7 +
separate patch
...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 +++++++++++++++++
separate patch
.../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
squash with SPL support patch.
Will update all in v7.
Jagan.