Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/armv7/mx5/clock.c | 26 +++----------------- 1 file changed, 3 insertions(+), 23 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index 75a6eae..0801e4f 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c @@ -430,7 +430,7 @@ static u32 get_uart_clk(void) */ static u32 imx_get_cspiclk(void) { - u32 ret_val = 0, pdf, pre_pdf, clk_sel; + u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
@@ -440,28 +440,8 @@ static u32 imx_get_cspiclk(void) >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; - - switch (clk_sel) { - case 0: - ret_val = decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_SYS_MX5_HCLK) / - ((pre_pdf + 1) * (pdf + 1)); - break; - case 1: - ret_val = decode_pll(mxc_plls[PLL2_CLOCK], - CONFIG_SYS_MX5_HCLK) / - ((pre_pdf + 1) * (pdf + 1)); - break; - case 2: - ret_val = decode_pll(mxc_plls[PLL3_CLOCK], - CONFIG_SYS_MX5_HCLK) / - ((pre_pdf + 1) * (pdf + 1)); - break; - default: - ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); - break; - } - + freq = get_standard_pll_sel_clk(clk_sel); + ret_val = freq / ((pre_pdf + 1) * (pdf + 1)); return ret_val; }