From: Nagabhushana Netagunte nagabhushana.netagunte@ti.com
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will.
Signed-off-by: Rajashekhara, Sudhakar sudhakar.raj@ti.com Signed-off-by: Nagabhushana Netagunte nagabhushana.netagunte@ti.com --- arch/arm/include/asm/arch-davinci/hardware.h | 5 ++++- board/davinci/da8xxevm/da850evm.c | 15 +++++++++++++++ 2 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index c41d756..3d6cb88 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -157,7 +157,10 @@ typedef volatile unsigned int * dv_reg_p; #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
- +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index fd05703..a077368 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -110,6 +110,8 @@ const struct pinmux_config nand_pins[] = { }; #elif defined(CONFIG_SYS_USE_NOR) const struct pinmux_config nor_pins[] = { + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ { pinmux(5), 1, 6 }, { pinmux(6), 1, 6 }, { pinmux(7), 1, 0 }, @@ -229,6 +231,7 @@ u32 get_board_rev(void)
int board_init(void) { + unsigned int val; #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -276,6 +279,18 @@ int board_init(void) if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1;
+#ifdef CONFIG_SYS_USE_NOR + /* Set the GPIO direction as output */ + val = REG(GPIO_BANK0_REG_DIR_ADDR); + val &= ~(0x01 << 11); + REG(GPIO_BANK0_REG_DIR_ADDR) = val; + + /* Set the output as low */ + val = REG(GPIO_BANK0_REG_SET_ADDR); + val |= (0x01 << 11); + REG(GPIO_BANK0_REG_CLR_ADDR) = val; +#endif + #ifdef CONFIG_DRIVER_TI_EMAC if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) return 1;