There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- tools/sunxi_egon.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c index af649c392e..0fff25843f 100644 --- a/tools/sunxi_egon.c +++ b/tools/sunxi_egon.c @@ -19,7 +19,7 @@ static int egon_check_params(struct image_tool_params *params) int arch;
/* Assume ARM when no architecture specified for compatibility */ - if (params->Aflags) + if (params->Aflag) arch = params->arch; else arch = IH_ARCH_ARM; @@ -27,8 +27,9 @@ static int egon_check_params(struct image_tool_params *params) /* * Check whether the architecture is supported. */ - switch(params->arch) { + switch(arch) { case IH_ARCH_ARM: + case IH_ARCH_RISCV: break; default: return EXIT_FAILURE; @@ -46,7 +47,7 @@ static int egon_verify_header(unsigned char *ptr, int image_size, int arch;
/* Assume ARM when no architecture specified for compatibility */ - if (params->Aflags) + if (params->Aflag) arch = params->arch; else arch = IH_ARCH_ARM; @@ -55,11 +56,15 @@ static int egon_verify_header(unsigned char *ptr, int image_size, * First 4 bytes must be a branch instruction of the corresponding * architecture. */ - switch(params->arch) { + switch(arch) { case IH_ARCH_ARM: if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000) return EXIT_FAILURE; break; + case IH_ARCH_RISCV: + if ((le32_to_cpu(header->b_instruction) & 0x00000fff) != 0x0000006f) + return EXIT_FAILURE; + break; default: return EXIT_FAILURE; /* Unknown architecture */ } @@ -113,7 +118,7 @@ static void egon_set_header(void *buf, struct stat *sbuf, int infd, int arch;
/* Assume ARM when no architecture specified for compatibility */ - if (params->Aflags) + if (params->Aflag) arch = params->arch; else arch = IH_ARCH_ARM; @@ -122,12 +127,30 @@ static void egon_set_header(void *buf, struct stat *sbuf, int infd, * Different architectures need different first instruction to * branch to the body. */ - switch (params->arch) { + switch (arch) { case IH_ARCH_ARM: /* Generate an ARM branch instruction to jump over the header. */ value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2); header->b_instruction = cpu_to_le32(value); break; + case IH_ARCH_RISCV: + /* + * Generate a RISC-V JAL instruction with rd=x0 + * (pseudo instruction J, jump without side effects). + * + * The following weird bit operation maps imm[20] + * to inst[31], imm[10:1] to inst[30:21], + * imm[11] to inst[20], imm[19:12] to inst[19:12], + * and imm[0] is dropped (because 1-byte RISC-V instruction + * is not allowed). + */ + value = 0x0000006f | + ((sizeof(struct boot_file_head) & 0x00100000) << 11) | + ((sizeof(struct boot_file_head) & 0x000007fe) << 20) | + ((sizeof(struct boot_file_head) & 0x00000800) << 9) | + ((sizeof(struct boot_file_head) & 0x000ff000) << 0); + header->b_instruction = cpu_to_le32(value); + break; }
memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));