Change the clock source of the SDHCI's generated clock from PLLA to UPLL clock to align to Linux driver.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com ---
board/atmel/sama5d2_xplained/sama5d2_xplained.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 10edf28..7324c2c 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -174,7 +174,7 @@ static void board_sdhci0_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_SDMMC0); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); }
static void board_sdhci1_hw_init(void) @@ -190,7 +190,7 @@ static void board_sdhci1_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_SDMMC1); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); }
int board_mmc_init(bd_t *bis)