From: Bastian Ruppert Bastian.Ruppert@Sewerin.de
Signed-off-by: Bastian Ruppert Bastian.Ruppert@Sewerin.de Signed-off-by: Stefano Babic sbabic@denx.de CC: dzu@denx.de CC: Sandeep Paulraj s-paulraj@ti.com --- arch/arm/include/asm/arch-davinci/hardware.h | 4 +++ board/davinci/ea20/ea20.c | 30 +++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 1892f15..ea61913 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -156,6 +156,10 @@ typedef volatile unsigned int * dv_reg_p; #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) #define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44) +#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88) +#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c) +#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90) +#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94) #endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */ diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 4e4107a..d1b56bf 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -34,6 +34,7 @@ #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> +#include <asm/arch/gpio_defs.h> #include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR; @@ -90,6 +91,12 @@ const struct pinmux_config nand_pins[] = { }; #endif
+const struct pinmux_config gpio_pins[] = { + { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/ + { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/ + { pinmux(13), 8, 3 } /* GPIO6[12] U0_SW1 on EA20-00101_2*/ +}; + static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_SPI_FLASH PINMUX_ITEM(spi1_pins), @@ -110,11 +117,32 @@ static const struct lpsc_resource lpsc[] = {
int board_init(void) { + struct davinci_gpio *gpio6_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK67; + + /* PinMux for GPIO */ + if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) + return 1; + + /* Set the RESETOUTn low */ + writel((readl(&gpio6_base->set_data) & ~(1 << 15)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir); + + /* Set U0_SW0 low for UART0 as console*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 10)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir); + + /* Set U0_SW1 low for UART0 as console*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 12)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir); + #ifndef CONFIG_USE_IRQ irq_init(); #endif
- #ifdef CONFIG_NAND_DAVINCI /* * NAND CS setup - cycle counts based on da850evm NAND timings in the