BSP boot0 adjust PLL LDO regulator before clocks are initialized. Let's do that.
Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com --- arch/arm/mach-sunxi/clock_sun50i_h6.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 32119ad16555..7926394cf762 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -21,6 +21,13 @@ void clock_init_safe(void) clrbits_le32(&prcm->res_cal_ctrl, 1); setbits_le32(&prcm->res_cal_ctrl, 1);
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + /* set key field for ldo enable */ + setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000); + /* set PLL VDD LDO output to 1.14 V */ + setbits_le32(&prcm->pll_ldo_cfg, 0x60000); + } + clock_set_pll1(408000000);
writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);