From: Camelia Groza camelia.groza@nxp.com
Starting with board revision D, the MISCCSR CPLD register needs to be configured to enable Power-on Reset for software reset commands.
Signed-off-by: Camelia Groza camelia.groza@nxp.com --- board/freescale/t208xrdb/cpld.h | 4 ++++ board/freescale/t208xrdb/t208xrdb.c | 7 +++++++ 2 files changed, 11 insertions(+)
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index a623b1811faf..3139c2b85fd1 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor + * Copyright 2021 NXP */
/* @@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value);
/* RSTCON Register */ #define CPLD_RSTCON_EDC_RST 0x04 + +/* MISCCSR Register */ +#define CPLD_MISC_POR_EN 0x30 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 1f0cdee0b863..947dd6aa9f3a 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -128,6 +128,13 @@ int misc_init_r(void) reg |= CPLD_RSTCON_EDC_RST; CPLD_WRITE(reset_ctl, reg);
+ /* Enable POR for boards revisions D and up */ + if (get_hw_revision() >= 'D') { + reg = CPLD_READ(misc_csr); + reg |= CPLD_MISC_POR_EN; + CPLD_WRITE(misc_csr, reg); + } + return 0; }