Signed-off-by: Vipin vipin.kumar@st.com --- board/spear/common/spr_misc.c | 60 +++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_emi.h | 54 ++++++++++++++++++++++ include/configs/spear.h | 82 ++++++++++++++++++++++++++++++--- 3 files changed, 188 insertions(+), 8 deletions(-) create mode 100644 include/asm-arm/arch-spear/spr_emi.h
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 391cec2..8153123 100755 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -26,6 +26,7 @@ #include <i2c.h> #include <net.h> #include <asm/io.h> +#include <asm/arch/spr_emi.h> #include <asm/arch/spr_xloader_table.h> #include <asm/arch/spr_defs.h>
@@ -79,6 +80,62 @@ int misc_init_r(void) return 0; }
+#ifdef CONFIG_SPEAR_EMI +struct cust_emi_para { + unsigned int tap; + unsigned int tsdp; + unsigned int tdpw; + unsigned int tdpr; + unsigned int tdcs; + unsigned int control; +}; + +/* EMI timing setting of m28w640hc of linux kernel */ +const struct cust_emi_para emi_timing_m28w640hc = { + .tap = 0x10, + .tsdp = 0x05, + .tdpw = 0x0a, + .tdpr = 0x0a, + .tdcs = 0x05, +}; + +/* EMI timing setting of bootrom */ +const struct cust_emi_para emi_timing_bootrom = { + .tap = 0xf, + .tsdp = 0x0, + .tdpw = 0xff, + .tdpr = 0x111, + .tdcs = 0x02, +}; + +void spear_emi_init(void) +{ + const struct cust_emi_para *p = &emi_timing_m28w640hc; + struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE; + unsigned int cs; + unsigned int val, tmp; + + val = readl(CONFIG_SPEAR_RASBASE); + + if (val & EMI_ACKMSK) + tmp = 0x3f; + else + tmp = 0x0; + + writel(tmp, &emi_regs_p->ack); + + for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { + writel(p->tap, &emi_regs_p->bank_regs[cs].tap); + writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); + writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); + writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); + writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); + writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), + &emi_regs_p->bank_regs[cs].control); + } +} +#endif + int spear_board_init(ulong mach_type) { struct xloader_table *xloader_tb = @@ -100,6 +157,9 @@ int spear_board_init(ulong mach_type) sizeof(chip->version)); }
+#ifdef CONFIG_SPEAR_EMI + spear_emi_init(); +#endif return 0; }
diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h new file mode 100644 index 0000000..c1f1c2a --- /dev/null +++ b/include/asm-arm/arch-spear/spr_emi.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPEAR_EMI_H__ +#define __SPEAR_EMI_H__ + +#ifdef CONFIG_SPEAR_EMI + +struct emi_bank_regs { + u32 tap; + u32 tsdp; + u32 tdpw; + u32 tdpr; + u32 tdcs; + u32 control; +}; + +struct emi_regs { + struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; + u32 tout; + u32 ack; + u32 irq; +}; + +#define EMI_ACKMSK 0x40 + +/* control register definitions */ +#define EMI_CNTL_ENBBYTEW (1 << 2) +#define EMI_CNTL_ENBBYTER (1 << 3) +#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) + +#endif + +#endif diff --git a/include/configs/spear.h b/include/configs/spear.h index 4e0a3dc..78c035f 100755 --- a/include/configs/spear.h +++ b/include/configs/spear.h @@ -64,7 +64,11 @@ /* * SMI driver configuration */ -#define CONFIG_SPEARSMI +#if defined(CONFIG_FLASH_PNOR) +#define CONFIG_SPEAR_EMI 1 +#else +#define CONFIG_SPEARSMI 1 +#endif
/* * Serial Configuration (PL011) @@ -125,7 +129,6 @@ #define CONFIG_SYS_PLUG_BASE (0xE1200000) #define CONFIG_SYS_FIFO_BASE (0xE1000800) #define CONFIG_SYS_SMI_BASE (0xFC000000) -#define CONFIG_SYS_FLASH_BASE (0xF8000000) #define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) #define CONFIG_SPEAR_TIMERBASE (0xFC800000) #define CONFIG_SPEAR_MISCBASE (0xFCA80000) @@ -153,11 +156,17 @@ #define CONFIG_SYS_NAND_CLE (1 << 17) #define CONFIG_SYS_NAND_ALE (1 << 16)
+#define CONFIG_SPEAR_EMIBASE (0x4F000000) +#define CONFIG_SPEAR_RASBASE (0xB4000000) + #elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) #define CONFIG_SPEAR_FSMCBASE (0x4C000000) #define CONFIG_SYS_NAND_BASE (0x50000000)
+#define CONFIG_SPEAR_EMIBASE (0x40000000) +#define CONFIG_SPEAR_RASBASE (0xB3000000) + #endif
#define CONFIG_SYS_HZ (1000) @@ -166,6 +175,8 @@ /* * FLASH Configuration */ +#if defined(CONFIG_SPEARSMI) + #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BASE (0xF8000000) #define CONFIG_SYS_CS1_FLASH_BASE (0xF9000000) @@ -178,6 +189,44 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
+#elif defined(CONFIG_SPEAR_EMI) + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#if defined(CONFIG_SPEAR310) +#define CONFIG_SYS_FLASH_BASE 0x50000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000 +#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000 +#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE, \ + CONFIG_SYS_CS4_FLASH_BASE, \ + CONFIG_SYS_CS5_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 6 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FLASH_BASE 0x44000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 4 + +#endif + +#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) +#define CONFIG_SYS_FLASH_QUIET_TEST 1 + +#endif + /* * NAND FLASH Configuration */ @@ -215,26 +264,43 @@ * U-Boot Environment placing definitions. */ #if defined(CONFIG_ENV_IS_IN_FLASH) +#ifdef CONFIG_SPEARSMI +/* + * Environment is in serial NOR flash + */ #define CONFIG_SYS_MONITOR_LEN 0x00040000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 #define CONFIG_FSMTDBLK "/dev/mtdblock8 " -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN)
#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
+#elif defined(CONFIG_SPEAR_EMI) +/* + * Environment is in parallel NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00060000 +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#define CONFIG_FSMTDBLK "/dev/mtdblock3 " + +#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \ + "0x4C0000; bootm 0x1600000" +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) #elif defined(CONFIG_ENV_IS_IN_NAND) +/* + * Environment is in NAND + */
#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_SIZE 0x04000 #define CONFIG_ENV_RANGE 0x10000 #define CONFIG_FSMTDBLK "/dev/mtdblock12 "
#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ "0x80000 0x4C0000; " \ "bootm 0x1600000" - #endif
#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \