On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers.
But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
I don't think it is appropriate to use raw timing for this application. This board use DIMMs, not soldered DDR chips. In normal cases, this piece of code is not used. It is only useful if you have a DIMM without a valid SPD. You could get another DIMM. I am not saying this patch is wrong, it is just useless for general public.
York