5 May
2015
5 May
'15
6:32 p.m.
On 03/26/2015 10:24 PM, Minghuan Lian wrote:
Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version.
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com Signed-off-by: Roy Zang tie-fei.zang@freescale.com Signed-off-by: Minghuan Lian Minghuan.Lian@freescale.com
Applied to u-boot-mpc85xx master. Awaiting upstream.
York