Re: [PATCH 06/13] clk/qcom: sdm845: add USB clocks

On Wed, Jan 31, 2024 at 03:16:58PM +0000, Caleb Connolly wrote:

@@ -121,6 +130,26 @@ static int sdm845_clk_enable(struct clk *clk)

debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);

• switch (clk->id) {
• case GCC_USB30_PRIM_MASTER_CLK:

• gdsc_enable(priv->base + USB30_PRIM_GDSCR);
  

• qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
  

• /* These numbers are just pulled from the frequency tables in the Linux driver */
  

• clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
  

• 		     (4.5 * 2) - 1, 0, 0, 1 << 8, 8);
  

• clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
  

• 		     1, 0, 0, 0, 8);
  

• clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
  

• 		     1, 0, 0, 0, 8);
  

• case GCC_USB30_SEC_MASTER_CLK:

Is this supposed to break? Otherwise can we add a "fallthrough;" annotation?

• gdsc_enable(priv->base + USB30_SEC_GDSCR);
  

• qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
  

• qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
  

• qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
  

• break;
  

• }

regards, dan carpenter