The initial serial console UART iomux is typically configured in board_debug_uart_init() at TPL stage on Rockchip platform.
Later stages typically use pinctrl driver to configure iomux UART once again based on the control FDT.
Include uart related pinctrl nodes in TPL/SPL control FDT to make it possible for pinctrl driver to configure UART iomux at TPL/SPL stage.
Following debug log message may also be seen at U-Boot pre-reloc stage:
ns16550_serial serial@ff1a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
This can be resolved by including bootph prop for U-Bood pre-reloc phase (bootph-some-ram or bootph-all). However, this has intentionally been excluded due to including it unnecessarily slows down boot around 200-400 ms.
Also add the clock-frequency prop similar to what has been done for other Rockchip SoCs.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: New patch split from "Fix loading FIT from SD-card" patch v2: Change to only include pinctrl nodes in TPL and SPL phase
Hopefully the clock-frequency prop can be used to help speed up boot in a future patch series, loading the uart rate from clock driver currently delays boot at i.e. U-Boot proper pre-reloc. --- arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 6 ++++++ 2 files changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index 390cf24152a6..d1912a2ef6a9 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -113,4 +113,20 @@
&uart0 { bootph-all; + clock-frequency = <24000000>; +}; + +&uart0_cts { + bootph-pre-sram; + bootph-pre-ram; +}; + +&uart0_rts { + bootph-pre-sram; + bootph-pre-ram; +}; + +&uart0_xfer { + bootph-pre-sram; + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 9815dc53e8ed..b39fe39fa2b3 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -136,6 +136,12 @@
&uart2 { bootph-all; + clock-frequency = <24000000>; +}; + +&uart2c_xfer { + bootph-pre-sram; + bootph-pre-ram; };
&vopb {