On 12.09.2015 17:20, Tom Rini wrote:
On Sat, Sep 12, 2015 at 09:46:51AM -0500, Scott Wood wrote:
On Sat, 2015-09-12 at 10:46 -0400, Tom Rini wrote:
On Sat, Sep 12, 2015 at 09:36:54AM -0500, Scott Wood wrote:
On Sat, 2015-09-12 at 08:50 -0400, Tom Rini wrote:
On Wed, Sep 02, 2015 at 02:29:12PM +0200, Stefan Roese wrote:
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your config header:
#define CONFIG_NAND_ECC_BCH #define CONFIG_BCH
And use the command "nandecc bch4" to select this ECC scheme upon runtime.
Tested on SPEAr600 x600 board.
Signed-off-by: Stefan Roese sr@denx.de Cc: Scott Wood scottwood@freescale.com Acked-by: Viresh Kumar viresh.kumar@linaro.org
Applied to u-boot/master, thanks!
There's a v3, and some minor comments even on that one...
Mutter, sorry. Would you rather a revert of the series or just incremental on top?
Either is fine -- I just wanted to make sure it didn't get forgotten.
OK, Stefan, please do an incremental on top of master now to cover what's been noted in v3, thanks!
Sure.
Thanks, Stefan