Hi,
Anders Larsen wrote on :
"Patrick .." oc3an@gmx.net schreibt:
Also, it is safe to use a divisor of 3 for the Master Clock, this gives 61.44MHz from a core of 184.32Mhz which is fine for the CSB637 (master clock limit is 80MHz), users should see a decent improvement in performance by doing this as it will increase the SDRAM bandwidth by a substantial amount.
Well, I got the clock values from linux 2.6.12 board-csb637.c; does Linux still boot correctly with your change?
I already posted this on the list, but a little reminder won't hurt :)
A clock rate > 180 MHz could be problematic. According errata 42 (AC Characteristics: PLL Frequency Limitation), in AT91RM9200 errata sheet (doc6015) the PLL is limited to 180 MHz. We already had problems with this bug (with about 10%-15% of the CPUs). After configuring the PLL for 179 MHz no errors occour any mor (before we used 207 MHz).
Regards, Martin