Re: [U-Boot] [PATCH v6] mx6sx: Add initial support for Samtec VIN|ING 2000 board

On 29/11/2016 16:13, Christoph Fritz wrote:

This patch adds initial support for Samtec VIN|ING 2000 board.

Signed-off-by: Christoph Fritz chf.fritz@googlemail.com

Changes since v1:

• add more comments (enet phy init)
• fix layout style e.g. multi-line-comments
• use pinmux macros
• use helper funcs clrsetbits_le32() and wait_for_bit()
• make some functions static
• drop board_ehci_hcd_init() and board_phy_config()
• simplify environment

Changes since v2:

• adapt error handling in board_eth_init() and read_adc()
• purge unused macros
• use config_distro_bootcmd as environment
• fix CONFIG_PWM_IMX undef handling

Changes since v3:

• fix comment spelling
• use u32
• rearrange if condition

Changes since v4:

• use parent error codes
• rename config string to TARGET_SAMTEC_VINING_2000

Changes since v5:

• simplify board_eth_init() error message

arch/arm/cpu/armv7/mx6/Kconfig | 7 + board/samtec/vining_2000/Kconfig | 12 + board/samtec/vining_2000/MAINTAINERS | 6 + board/samtec/vining_2000/Makefile | 6 + board/samtec/vining_2000/imximage.cfg | 132 +++++++++ board/samtec/vining_2000/vining_2000.c | 517 +++++++++++++++++++++++++++++++++ configs/vining_2000_defconfig | 31 ++ include/configs/vining_2000.h | 123 ++++++++ 8 files changed, 834 insertions(+) create mode 100644 board/samtec/vining_2000/Kconfig create mode 100644 board/samtec/vining_2000/MAINTAINERS create mode 100644 board/samtec/vining_2000/Makefile create mode 100644 board/samtec/vining_2000/imximage.cfg create mode 100644 board/samtec/vining_2000/vining_2000.c create mode 100644 configs/vining_2000_defconfig create mode 100644 include/configs/vining_2000.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 762a581..057b8cd 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -192,6 +192,12 @@ config TARGET_UDOO bool "udoo" select SUPPORT_SPL

+config TARGET_SAMTEC_VINING_2000

• bool "samtec VIN|ING 2000"
• select MX6SX
• select DM
• select DM_THERMAL

config TARGET_WANDBOARD bool "wandboard" select SUPPORT_SPL @@ -247,6 +253,7 @@ source "board/freescale/mx6ullevk/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" +source "board/samtec/vining_2000/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig new file mode 100644 index 0000000..3447c27 --- /dev/null +++ b/board/samtec/vining_2000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAMTEC_VINING_2000

+config SYS_BOARD

• default "vining_2000"

+config SYS_VENDOR

• default "samtec"

+config SYS_CONFIG_NAME

• default "vining_2000"

+endif diff --git a/board/samtec/vining_2000/MAINTAINERS b/board/samtec/vining_2000/MAINTAINERS new file mode 100644 index 0000000..027e527 --- /dev/null +++ b/board/samtec/vining_2000/MAINTAINERS @@ -0,0 +1,6 @@ +VINING_2000 BOARD +M: Ingo Schroeck open-source@samtec.de +S: Maintained +F: board/samtec/vining_2000/ +F: include/configs/vining_2000.h +F: configs/vining_2000_defconfig diff --git a/board/samtec/vining_2000/Makefile b/board/samtec/vining_2000/Makefile new file mode 100644 index 0000000..1b32f66 --- /dev/null +++ b/board/samtec/vining_2000/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 samtec automotive software & electronics gmbh +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y := vining_2000.o diff --git a/board/samtec/vining_2000/imximage.cfg b/board/samtec/vining_2000/imximage.cfg new file mode 100644 index 0000000..4133dda --- /dev/null +++ b/board/samtec/vining_2000/imximage.cfg @@ -0,0 +1,132 @@ +/*

• • Copyright (C) 2016 samtec automotive software & electronics gmbh
• • SPDX-License-Identifier: GPL-2.0+
• */

+#define __ASSEMBLY__ +#include <config.h>

+/* image version */

+IMAGE_VERSION 2

+/*

• • Boot Device : one of
• • spi/sd/nand/onenand, qspi/nor
• */

+BOOT_FROM sd

+/*

• • Device Configuration Data (DCD)
• • Each entry must have the format:
• • Addr-type Address Value
• • where:
• • Addr-type register length (1,2 or 4 bytes)
• • Address absolute address of the register
• • value value to be stored in the register
• */

+/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff

+/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000

+/* Clock */ +DATA 4 0x020e032c 0x00000030

+/* Address */ +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028

+/* Control */ +DATA 4 0x020e0340 0x00000028

+DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000028 +DATA 4 0x020e0314 0x00000028 +DATA 4 0x020e0614 0x00000028

+/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000028 +DATA 4 0x020e0334 0x00000028 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e033c 0x00000028

+/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028

+/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003

+/* Write leveling */ +DATA 4 0x021b080c 0x00290025 +DATA 4 0x021b0810 0x00210022

+/* DQS Read Gate */ +DATA 4 0x021b083c 0x4142013a +DATA 4 0x021b0840 0x012e0123

+/* Read/Write Delay */ +DATA 4 0x021b0848 0x43474949 +DATA 4 0x021b0850 0x38383c38

+/* Read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333

+/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800

+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333040 +DATA 4 0x021b000c 0x676b52f2 +DATA 4 0x021b0010 0x926e8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000

+/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x02008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x15108030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040

+/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00007800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b001c 0x00000000 diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c new file mode 100644 index 0000000..c92f37c --- /dev/null +++ b/board/samtec/vining_2000/vining_2000.c @@ -0,0 +1,517 @@ +/*

• • Copyright (C) 2016 samtec automotive software & electronics gmbh
• • Author: Christoph Fritz chf.fritz@googlemail.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include <usb.h> +#include <usb/ehci-ci.h> +#include <pwm.h> +#include <wait_bit.h>

+DECLARE_GLOBAL_DATA_PTR;

+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \

• PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
• PAD_CTL_SRE_FAST)

+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \

• PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
• PAD_CTL_SRE_FAST)

+#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm

+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \

• PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
• PAD_CTL_SRE_FAST)

+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \

• PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
• PAD_CTL_DSE_40ohm)

+#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \

• PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)

+#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \

• PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
• PAD_CTL_SRE_FAST)

+#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \

• PAD_CTL_PKE)

+int dram_init(void) +{

• gd->ram_size = imx_ddr_size();
• return 0;

+}

+static iomux_v3_cfg_t const uart1_pads[] = {

• MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

+};

+static iomux_v3_cfg_t const usdhc2_pads[] = {

• MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
• MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),

+};

+static iomux_v3_cfg_t const usdhc4_pads[] = {

• MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
• MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

+};

+static iomux_v3_cfg_t const fec1_pads[] = {

• MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |

• MUX_MODE_SION,
  

• /* LAN8720 PHY Reset */
• MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static iomux_v3_cfg_t const pwm_led_pads[] = {

• MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
• MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
• MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */

+};

+static void setup_iomux_uart(void) +{

• imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));

+}

+#define PHY_RESET IMX_GPIO_NR(5, 9)

+int board_eth_init(bd_t *bis) +{

• struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
• int ret;
• unsigned char eth1addr[6];
• /* just to get secound mac address */
• imx_get_mac_from_fuse(1, eth1addr);
• if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))

• eth_setenv_enetaddr("eth1addr", eth1addr);
  

• imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
• /*

• * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
  

• * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
  

• * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
  

• */
  

• clrsetbits_le32(&iomuxc_regs->gpr[1],

• 	IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
  

• 	IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
  

• 	IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
  

• 	IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  

• ret = enable_fec_anatop_clock(0, ENET_50MHZ);
• if (ret)

• goto eth_fail;
  

• /* reset phy */
• gpio_direction_output(PHY_RESET, 0);
• mdelay(16);
• gpio_set_value(PHY_RESET, 1);
• mdelay(1);
• ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,

• 			IMX_FEC_BASE);
  

• if (ret)

• goto eth_fail;
  

• return ret;

+eth_fail:

• printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
• gpio_set_value(PHY_RESET, 0);
• return ret;

+}

+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = {

• .scl = {

• .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  

• .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  

• .gp = IMX_GPIO_NR(1, 0),
  

• },
• .sda = {

• .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  

• .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  

• .gp = IMX_GPIO_NR(1, 1),
  

• },

+};

+static struct pmic *pfuze_init(unsigned char i2cbus) +{

• struct pmic *p;
• int ret;
• u32 reg;
• ret = power_pfuze100_init(i2cbus);
• if (ret)

• return NULL;
  

• p = pmic_get("PFUZE100");
• ret = pmic_probe(p);
• if (ret)

• return NULL;
  

• pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
• printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
• /* Set SW1AB stanby volage to 0.975V */
• pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
• reg &= ~SW1x_STBY_MASK;
• reg |= SW1x_0_975V;
• pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
• /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
• pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
• reg &= ~SW1xCONF_DVSSPEED_MASK;
• reg |= SW1xCONF_DVSSPEED_4US;
• pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
• /* Set SW1C standby voltage to 0.975V */
• pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
• reg &= ~SW1x_STBY_MASK;
• reg |= SW1x_0_975V;
• pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
• /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
• pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
• reg &= ~SW1xCONF_DVSSPEED_MASK;
• reg |= SW1xCONF_DVSSPEED_4US;
• pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
• return p;

+}

+static int pfuze_mode_init(struct pmic *p, u32 mode) +{

• unsigned char offset, i, switch_num;
• u32 id;
• int ret;
• pmic_reg_read(p, PFUZE100_DEVICEID, &id);
• id = id & 0xf;
• if (id == 0) {

• switch_num = 6;
  

• offset = PFUZE100_SW1CMODE;
  

• } else if (id == 1) {

• switch_num = 4;
  

• offset = PFUZE100_SW2MODE;
  

• } else {

• printf("Not supported, id=%d\n", id);
  

• return -EINVAL;
  

• }
• ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
• if (ret < 0) {

• printf("Set SW1AB mode error!\n");
  

• return ret;
  

• }
• for (i = 0; i < switch_num - 1; i++) {

• ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
  

• if (ret < 0) {
  

• 	printf("Set switch 0x%x mode error!\n",
  

• 	       offset + i * SWITCH_SIZE);
  

• 	return ret;
  

• }
  

• }
• return ret;

+}

+int power_init_board(void) +{

• struct pmic *p;
• int ret;
• p = pfuze_init(I2C_PMIC);
• if (!p)

• return -ENODEV;
  

• ret = pfuze_mode_init(p, APS_PFM);
• if (ret < 0)

• return ret;
  

• return 0;

+}

+#ifdef CONFIG_USB_EHCI_MX6 +static iomux_v3_cfg_t const usb_otg_pads[] = {

• /* OGT1 */
• MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* OTG2 */
• MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)

+};

+static void setup_iomux_usb(void) +{

• imx_iomux_v3_setup_multiple_pads(usb_otg_pads,

• 			 ARRAY_SIZE(usb_otg_pads));
  

+}

+int board_usb_phy_mode(int port) +{

• if (port == 1)

• return USB_INIT_HOST;
  

• else

• return usb_phy_mode(port);
  

+} +#endif

+#ifdef CONFIG_PWM_IMX +static int set_pwm_leds(void) +{

• int ret;
• imx_iomux_v3_setup_multiple_pads(pwm_led_pads,

• 			 ARRAY_SIZE(pwm_led_pads));
  

• /* enable backlight PWM 2, green LED */
• ret = pwm_init(1, 0, 0);
• if (ret)

• goto error;
  

• /* duty cycle 200ns, period: 8000ns */
• ret = pwm_config(1, 200, 8000);
• if (ret)

• goto error;
  

• ret = pwm_enable(1);
• if (ret)

• goto error;
  

• /* enable backlight PWM 1, blue LED */
• ret = pwm_init(0, 0, 0);
• if (ret)

• goto error;
  

• /* duty cycle 200ns, period: 8000ns */
• ret = pwm_config(0, 200, 8000);
• if (ret)

• goto error;
  

• ret = pwm_enable(0);
• if (ret)

• goto error;
  

• /* enable backlight PWM 6, red LED */
• ret = pwm_init(5, 0, 0);
• if (ret)

• goto error;
  

• /* duty cycle 200ns, period: 8000ns */
• ret = pwm_config(5, 200, 8000);
• if (ret)

• goto error;
  

• ret = pwm_enable(5);

+error:

• return ret;

+} +#else +static int set_pwm_leds(void) +{

• return 0;

+} +#endif

+#define ADCx_HC0 0x00 +#define ADCx_HS 0x08 +#define ADCx_HS_C0 BIT(0) +#define ADCx_R0 0x0c +#define ADCx_CFG 0x14 +#define ADCx_CFG_SWMODE 0x308 +#define ADCx_GC 0x18 +#define ADCx_GC_CAL BIT(7)

+static int read_adc(u32 *val) +{

• int ret;
• void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
• /* use software mode */
• writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
• /* start auto calibration */
• setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
• ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
• if (ret)

• goto adc_exit;
  

• /* start conversion */
• writel(0, b + ADCx_HC0);
• /* wait for conversion */
• ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
• if (ret)

• goto adc_exit;
  

• /* read result */
• *val = readl(b + ADCx_R0);

+adc_exit:

• if (ret)

• printf("ADC failure (ret=%i)\n", ret);
  

• unmap_physmem(b, MAP_NOCACHE);
• return ret;

+}

+#define VAL_UPPER 2498 +#define VAL_LOWER 1550

+static int set_pin_state(void) +{

• u32 val;
• int ret;
• ret = read_adc(&val);
• if (ret)

• return ret;
  

• if (val >= VAL_UPPER)

• setenv("pin_state", "connected");
  

• else if (val < VAL_UPPER && val > VAL_LOWER)

• setenv("pin_state", "open");
  

• else

• setenv("pin_state", "button");
  

• return ret;

+}

+int board_late_init(void) +{

• int ret;
• ret = set_pwm_leds();
• if (ret)

• return ret;
  

• ret = set_pin_state();
• return ret;

+}

+int board_early_init_f(void) +{

• setup_iomux_uart();
• setup_iomux_usb();
• return 0;

+}

+static struct fsl_esdhc_cfg usdhc_cfg[2] = {

• {USDHC4_BASE_ADDR, 0, 8},
• {USDHC2_BASE_ADDR, 0, 4},

+};

+#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)

+int board_mmc_getcd(struct mmc *mmc) +{

• struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
• if (cfg->esdhc_base == USDHC4_BASE_ADDR)

• return 1;
  

• if (cfg->esdhc_base == USDHC2_BASE_ADDR)

• return !gpio_get_value(USDHC2_CD_GPIO);
  

• return -EINVAL;

+}

+int board_mmc_init(bd_t *bis) +{

• int ret;
• /*

• * According to the board_mmc_init() the following map is done:
  

• * (U-Boot device node)    (Physical Port)
  

• * mmc0                    USDHC4
  

• * mmc1                    USDHC2
  

• */
  

• imx_iomux_v3_setup_multiple_pads(

• usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  

• usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
• imx_iomux_v3_setup_multiple_pads(

• usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  

• gpio_direction_input(USDHC2_CD_GPIO);
• usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
• ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
• if (ret) {

• printf("Warning: failed to initialize USDHC4\n");
  

• return ret;
  

• }
• ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
• if (ret) {

• printf("Warning: failed to initialize USDHC2\n");
  

• return ret;
  

• }
• return 0;

+}

+int board_init(void) +{

• /* Address of boot parameters */
• gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

+#ifdef CONFIG_SYS_I2C_MXC

• setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

+#endif

• return 0;

+}

+int checkboard(void) +{

• puts("Board: VIN|ING 2000\n");
• return 0;

+} diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig new file mode 100644 index 0000000..b1f64f1 --- /dev/null +++ b/configs/vining_2000_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_SAMTEC_VINING_2000=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/samtec/vining_2000/imximage.cfg" +CONFIG_BOOTDELAY=0 +CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_PCI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_USB_OTG_HACTIVE=y diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h new file mode 100644 index 0000000..235574d --- /dev/null +++ b/include/configs/vining_2000.h @@ -0,0 +1,123 @@ +/*

• • Copyright (C) 2016 samtec automotive software & electronics gmbh
• • Configuration settings for the Samtec VIN|ING 2000 board.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __CONFIG_H +#define __CONFIG_H

+#include "mx6_common.h"

+#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif

+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)

+#define CONFIG_BOARD_EARLY_INIT_F

+#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE

+#define BOOT_TARGET_DEVICES(func) \

• func(MMC, mmc, 0) \
• func(MMC, mmc, 1) \
• func(USB, usb, 0) \
• func(PXE, pxe, na) \
• func(DHCP, dhcp, na)

+#include <config_distro_bootcmd.h>

+/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)

+#define CONFIG_STACKSIZE SZ_128K

+/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR

+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

+#define CONFIG_SYS_INIT_SP_OFFSET \

• (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

+#define CONFIG_SYS_INIT_SP_ADDR \

• (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

+/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR

+/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000

+/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08

+/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII

+#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0

+#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC"

+#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS

+#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif

+#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) +#endif

+#define CONFIG_IMX_THERMAL

+#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 +#define CONFIG_BOARD_LATE_INIT

+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_IS_IN_MMC

+#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */ +/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ +#endif

+#endif /* __CONFIG_H */

Reviewed-by: Stefano Babic sbabic@denx.de

Best regards, Stefano Babic