
28 Jul
2020
28 Jul
'20
9:01 p.m.
Hi Stefan,
On Fri, 24 Jul 2020 at 04:09, Stefan Roese sr@denx.de wrote:
From: Suneel Garapati sgarapati@marvell.com
Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus.
Signed-off-by: Suneel Garapati sgarapati@marvell.com Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com
Signed-off-by: Stefan Roese sr@denx.de
Changes in v1:
- Change patch subject
- Enhance Kconfig help descrition
- Use if() instead of #if
drivers/pci/Kconfig | 10 ++++++++++ drivers/pci/pci-uclass.c | 9 ++++++--- 2 files changed, 16 insertions(+), 3 deletions(-)
This needs an update to a sandbox test to handle this behaviour.