Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng [mailto:bmeng.cn@gmail.com] Sent: 2019年4月1日 13:32 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; albert.u.boot@aribaud.net; Priyanka Jain priyanka.jain@nxp.com; York Sun york.sun@nxp.com; yamada.masahiro@socionext.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Mingkai Hu mingkai.hu@nxp.com; M.h. Lian minghuan.lian@nxp.com Subject: Re: [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries for PCIe
Hi Zhiqiang,
On Mon, Apr 1, 2019 at 12:08 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng [mailto:bmeng.cn@gmail.com] Sent: 2019年4月1日 11:22 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; albert.u.boot@aribaud.net; Priyanka Jain priyanka.jain@nxp.com; York Sun york.sun@nxp.com; sriram.dash@nxp.com; yamada.masahiro@socionext.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Mingkai Hu mingkai.hu@nxp.com; M.h. Lian minghuan.lian@nxp.com Subject: Re: [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries for PCIe
On Mon, Mar 25, 2019 at 10:24 AM Z.q. Hou zhiqiang.hou@nxp.com
wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V4:
- No change
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12
++++++++++++
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 14 +++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b32f..2805e5f6f2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -257,6 +257,18 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN |
PTE_BLOCK_UXN
},+#endif +#ifdef CONFIG_ARCH_LX2160A
{ SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,SYS_PCIE5_PHYS_SIZE,PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN |PTE_BLOCK_UXN
},{ SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,SYS_PCIE6_PHYS_SIZE,PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN |PTE_BLOCK_UXN
},#endif { CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_SIZE, diff --gita/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 89124cdb0e..bdeb62576c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -44,6 +44,8 @@ #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 +#define SYS_PCIE5_PHYS_SIZE 0x800000000 +#define SYS_PCIE6_PHYS_SIZE 0x800000000
Why are these macros not CONFIG_ prefixed?
The new added macros with prefix CONFIG_ will result in build error, so we
don't add the CONFIG_ prefix.
I am curious how can such prefix cause build error?
It looks like the CFGCHK scripts reports the error as following: CFGCHK u-boot.cfg Error: You must add new CONFIG options using Kconfig The following new ad-hoc CONFIG options were detected: CONFIG_SYS_PCIE5_ADDR
Regards, Bin
Thanks, Zhiqiang