From: Soren Brinkmann soren.brinkmann@xilinx.com
Signed-off-by: Soren Brinkmann soren.brinkmann@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com --- drivers/serial/serial_zynq.c | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 050b9c0..ff28f3c 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -21,10 +21,6 @@
#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
-/* Some clock/baud constants */ -#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ -#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ - struct uart_zynq { u32 control; /* Control Register [8:0] */ u32 mode; /* Mode Register [10:0] */ -- 1.8.2.3