On 26 September 2016 at 12:29, Paul Burton paul.burton@imgtec.com wrote:
On the MIPS Boston development board we have an Intel EG20T Platform Controller Hub connected to a Xilinx AXI to PCIe root port which is only assigned a 1MB memory region. The Intel EG20T contains a bridge device beneath which all of its peripheral devices can be found, and that bridge device contains a ROM. If we align to 1MB when we encounter each bridge device we therefore do something like this:
Start with bus_lower at 0x16000000.
Find the Xilinx root bridge, which has no visible BARs so we do very little to it.
Probe the bus beneath the Xilinx bridge device, aligning bus_lower to a 1MB boundary first. That leaves it still at 0x16000000.
Find the EG20T bridge device, which we find has a 64KiB ROM. We assign it the address range 0x16000000-0x1600ffff which leaves bus_lower at 0x16010000.
Probe the bus beneath the EG20T bridge device, aligning bus_lower to a 1MB boundary first. This leaves bus_lower at 0x16100000, which is the end of the available memory space.
Find the various peripheral devices the EG20T contains, but fail to assign any memory space to them since bus_lower is at the end of the memory space available to the PCI bus.
Fix this by disabling that 1MB alignment, which allows all of the EG20T peripheral devices to be assigned memory space within the 1MB region available.
Signed-off-by: Paul Burton paul.burton@imgtec.com
configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig | 1 + 4 files changed, 4 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org