sp805 is watchdog on some NXP layerscape SoCs, Now add its driver in uboot.
Signed-off-by: Zhao Qiang qiang.zhao@nxp.com --- MAINTAINERS | 1 + common/board_f.c | 2 +- drivers/watchdog/Kconfig | 8 +++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/sp805_wdt.c | 70 ++++++++++++++++++++++++++++++++++++ 5 files changed, 81 insertions(+), 1 deletion(-) create mode 100644 drivers/watchdog/sp805_wdt.c
diff --git a/MAINTAINERS b/MAINTAINERS index 8f237128b2..e8e7a92802 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -410,6 +410,7 @@ FREESCALE QORIQ M: York Sun york.sun@nxp.com S: Maintained T: git git://git.denx.de/u-boot-fsl-qoriq.git +F: drivers/watchdog/sp805_wdt.c
I2C M: Heiko Schocher hs@denx.de diff --git a/common/board_f.c b/common/board_f.c index 88d770071c..06bfff6e50 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -91,7 +91,7 @@ static int init_func_watchdog_init(void) (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ defined(CONFIG_DESIGNWARE_WATCHDOG) || \ - defined(CONFIG_IMX_WATCHDOG)) + defined(CONFIG_IMX_WATCHDOG) || defined(CONFIG_WDT_SP805)) hw_watchdog_init(); puts(" Watchdog enabled\n"); # endif diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b06c5447f6..9ca8c729b7 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -95,6 +95,14 @@ config WDT_ORION Select this to enable Orion watchdog timer, which can be found on some Marvell Armada chips.
+config WDT_SP805 + bool "SP805 watchdog timer support" + depends on FSL_LAYERSCAPE + select HW_WATCHDOG + help + Select this to enable SP805 watchdog timer, which can be found on some + nxp layerscape chips. + config WDT_CDNS bool "Cadence watchdog timer support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 19c631bb58..eb285bde24 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o +obj-$(CONFIG_WDT_SP805) += sp805_wdt.o diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c new file mode 100644 index 0000000000..64604a09e7 --- /dev/null +++ b/drivers/watchdog/sp805_wdt.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Watchdog driver for SP805 on some Layerscape SoC + * + * Copyright 2019 NXP + */ + +#include <asm/io.h> +#include <common.h> +#include <linux/bitops.h> +#include <watchdog.h> + +#define SP805_WDT_ADDR_BASE 0xc000000 +#define WDTLOAD 0x000 +#define WDTCONTROL 0x008 +#define WDTINTCLR 0x00C +#define WDTLOCK 0xC00 + +#define TIME_OUT_SECS 15 +#define SYS_FSL_WDT_CLK_DIV 16 +#define INT_ENABLE BIT(0) +#define RESET_ENABLE BIT(1) +#define UNLOCK 0x1ACCE551 +#define LOCK 0x00000001 +#define INT_MASK BIT(0) + +DECLARE_GLOBAL_DATA_PTR; + +void hw_watchdog_reset(void) +{ + writel(UNLOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + writel(INT_MASK, SP805_WDT_ADDR_BASE + WDTINTCLR); + writel(LOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + readl(SP805_WDT_ADDR_BASE + WDTLOCK); +} + +void hw_watchdog_init(void) +{ + u32 load_value; + /* sp805 runs counter with given value twice, so when the timeout is + * set 15s, the gd->bus_clk is less than 9162MHz, the load_value will + * not overflow. + */ + load_value = (TIME_OUT_SECS / 2) * (gd->bus_clk / SYS_FSL_WDT_CLK_DIV); + + writel(UNLOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + writel(load_value, SP805_WDT_ADDR_BASE + WDTLOAD); + writel(INT_MASK, SP805_WDT_ADDR_BASE + WDTINTCLR); + writel(INT_ENABLE | RESET_ENABLE, SP805_WDT_ADDR_BASE + WDTCONTROL); + writel(LOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + readl(SP805_WDT_ADDR_BASE + WDTLOCK); +} + +static int do_wdt_test(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + writel(UNLOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + writel(INT_MASK, SP805_WDT_ADDR_BASE + WDTINTCLR); + writel(LOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + readl(SP805_WDT_ADDR_BASE + WDTLOCK); + while (1) { + /* + * spin to test watchdog + */ + } + return 0; +} + +U_BOOT_CMD(wdt_test, 1, 1, do_wdt_test, "test watchdog", + "when run this command, the uboot will reset");