Hi Fabio, On Mon, Aug 29, 2016 at 12:20:12AM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.estevam@nxp.com
When running NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq.
Comparing the DDR calibration values against NXP U-Boot showed that the values were incorrect.
Adjust the calibration values so that we can avoid such system hang.
Reported-by: Eric Nelson eric@nelint.com Signed-off-by: Fabio Estevam fabio.estevam@nxp.com
Acked-by: Peng Fan peng.fan@nxp.com
Thanks, Peng.
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index c213861..77c561d 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -784,10 +784,10 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { };
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00070007,
- .p0_mpdgctrl0 = 0x41490145,
- .p0_mprddlctl = 0x40404546,
- .p0_mpwrdlctl = 0x4040524D,
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x41570155,
- .p0_mprddlctl = 0x4040474A,
- .p0_mpwrdlctl = 0x40405550,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
2.7.4
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