Gregory Hermant wrote:
The Calao USB-A9260 and USB-9G20 boards are manufactured and sold by Calao Systems http://www.calao-systems.com. They are built around an AT91SAM9260 ARM SoC running at 180MHz and an AT91SAM9G20 ARM SoC running at 400MHz respectively. They feature an Ethernet port, 64Mo of SDRAM, 256Mo of NAND flash, two USB host ports, and an USB device port. They also feature a FTDI2232 converter which provides the ability to use the DBGU serial port & the JTAG port over a USB interface.
Please run the linux kernel's checkpatch.pl program In general errors must be fixed. The warnings should be fixed when appropriate.
Signed-off-by: Gregory Hermant gregory.hermant@calao-systems.com
<snip>
+#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).a
+COBJS-y += usb_a9260.o +COBJS-$(CONFIG_ATMEL_SPI) += spi.o
Order alphabetically
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y))
<snip>
+#endif +#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+/* ------------------------------------------------------------------------- */ +/*
- Miscelaneous platform dependent initialisations
sp 'initializations'
- */
+#ifdef CONFIG_CMD_NAND +static void usb_a9260_nand_hw_init(void) +{
- unsigned long csa;
<snip>
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#ifdef CONFIG_USB_A9260 +#define CONFIG_AT91SAM9260 +#else +#define CONFIG_AT91SAM9G20 +#endif
+/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000
Move clock definitions below board/cpu definitions
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1
+#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT
+/*
- Hardware drivers
- */
+#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */
+#define CONFIG_BOOTDELAY 3
+/*
- BOOTP options
- */
+#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1
+/*
- Command line configuration.
- */
+#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE
+#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_USB 1
+/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
+/* SPI EEPROM */ +#define CONFIG_SPI +#define CONFIG_CMD_SPI +#define CONFIG_ATMEL_SPI +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
+#define CONFIG_CMD_EEPROM +#define CONFIG_SPI_M95XXX +#define CONFIG_SYS_EEPROM_SIZE 0x10000 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+/* NAND flash */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +//#define CONFIG_SYS_NAND_DBW_8 1
Remove if unneeded or uncomment
+/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
Tom