From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com
Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1.
Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Reviewed-by: Peter Crosthwaite peter.crosthwaite@xilinx.com Reviewed-by: Nathan Rossi nathan.rossi@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/cpu/armv7/zynq/slcr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 934ccc31c86f..2521589c07e9 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void) zynq_slcr_unlock();
/* Disable AXI interface by asserting FPGA resets */ - writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); + writel(0xF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */ writel(0xA, &slcr_base->lvl_shftr_en); -- 1.8.2.3