On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options.
Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.
The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 29 +++++++++++++++++++++++++++++ board/freescale/b4860qds/b4860qds.c | 2 ++ board/freescale/b4860qds/eth_b4860qds.c | 5 +++++ 3 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 6ff6a70..d7b5950 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -24,6 +24,8 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, CPRI2, CPRI1}}, {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, @@ -32,6 +34,9 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2F, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x30, {AURORA, AURORA, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, CPRI4, CPRI3, CPRI2, CPRI1}}, @@ -50,12 +55,18 @@ static struct serdes_config serdes1_cfg_tbl[] = { }; static struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ + {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1} }, {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, SRIO1, SRIO1}}, {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, SRIO1, SRIO1}}, + {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, SRIO1, SRIO1} }, {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, SRIO1, SRIO1}}, @@ -63,6 +74,9 @@ static struct serdes_config serdes2_cfg_tbl[] = { SRIO2, SRIO2, AURORA, AURORA, SRIO1, SRIO1}}, + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, SRIO1, SRIO1, SRIO1, SRIO1}}, @@ -75,18 +89,30 @@ static struct serdes_config serdes2_cfg_tbl[] = { {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x79, {SRIO2, SRIO2, SRIO2, SRIO2, + SRIO1, SRIO1, SRIO1, SRIO1} }, {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, XFI_FM1_MAC9, XFI_FM1_MAC10}}, {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, @@ -101,6 +127,9 @@ static struct serdes_config serdes2_cfg_tbl[] = { SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index f6b012d..901c956 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -120,6 +120,7 @@ int configure_vsc3316_3308(void) debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
switch (serdes1_prtcl) { + case 0x29: case 0x2a: case 0x2C: case 0x2D: @@ -152,6 +153,7 @@ int configure_vsc3316_3308(void) break;
#ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* * Configuration: diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index a8fc845..12df9a8 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -66,6 +66,7 @@ static void initialize_lane_to_slot(void) serdes2_prtcl);
switch (serdes2_prtcl) { + case 0x17: case 0x18: /* * Configuration: @@ -198,6 +199,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
switch (serdes1_prtcl) { + case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ debug("Setting phy addresses for FM1_DTSEC5: %x and" @@ -209,6 +211,7 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); break; #ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ debug("Setting phy addresses for FM1_DTSEC3: %x and" @@ -228,6 +231,7 @@ int board_eth_init(bd_t *bis) break; } switch (serdes2_prtcl) { + case 0x17: case 0x18: debug("Setting phy addresses on SGMII Riser card for" "FM1_DTSEC ports: \n"); @@ -240,6 +244,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); break; + case 0x48: case 0x49: debug("Setting phy addresses on SGMII Riser card for" "FM1_DTSEC ports: \n");