On Tue, Feb 7, 2012 at 11:52 AM, Scott Larson slarson@a2etech.com wrote:
Hi,
Looking for help on DDR2 configuration in u-boot.
I have the MPC8313ERDB from Freescale. It has 128Mbytes of DDR2 ram. The existing 128MByte that uses only CS0.
I have a new board design to bring up.
The timing parameters are all ok but I need some guidance on changing the settings to suit my memory configuration.
My board has 512Mbytes on CS0 and 512Mbytes on CS1.
Changes need to be made to files MPC8313ERDB.h and sdram.c
SODIMM with SPD? Autoconfig with CONFIG_SPD_EEPROM is nice compared to hard coding values, if you can use it. I'm pretty sure it works fine on sbc8349 board.
I have made all the row and column size and block address pin settings ok. I have set DDR size to 512Mbytes (per Chip Select).
I need some guidance on the setting for CS1 bank of ram.
Have you created the CONFIG_SYS_BR1_PRELIM and the CONFIG_SYS_OR1_PRELIM defines in your board header?
If you copied these from a reference platform, they may still be populated with settings appropriate for flash up at the top of memory instead of DDR2 settings for your 2nd bank...
P.
thanks
Scott
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