On Sab, 2017-06-03 at 13:29 +0200, Marek Vasut wrote:
On 05/29/2017 06:00 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Enable FPGA driver build for SPL because FPGA driver is needed for SPL to configure and getting DDR up before loading U-boot into DDR and booting from there.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
The thing I fail to understand is why you're sending the patches in seemingly random order. You add/change piece of code, then enable something and then add the relevant code you're enabling. I really do not understand that.
The patches should have some logical order -- change existing code, add new code, enable stuff.
Anyway, please collect the Acks, fix the nit and resubmit.
Sorry for confusing, i enabled the stuff just to detect any break and bugs as early as possible. I will follow the logical order next time :) .
drivers/Makefile | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/Makefile b/drivers/Makefile index 64c39d3..4478212 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += block/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ +obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/ endif ifdef CONFIG_TPL_BUILD