On Wed, Jan 19, 2011 at 5:04 PM, Peter Tyser ptyser@xes-inc.com wrote:
Hi Tom, Some last minutes nits:
It looks like some of the new functions can be declared statically. It'd be nice to do so where possible.
Which functions, Peter? Please point them out specifically, thanks.
<snip>
--- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -0,0 +1,66 @@ +/*
- Board specific setup info
This is CPU-specific code, correct?
Yes - I'll change the comment.
- (C) Copyright 2010,2011
- NVIDIA Corporation <www.nvidia.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <config.h> +#include <version.h>
+_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
+.global invalidate_dcache +invalidate_dcache:
- mov pc, lr
- .align 5
+.global reset_cpu +reset_cpu:
- ldr r1, rstctl @ get addr for global reset
- @ reg
- ldr r3, [r1]
- orr r3, r3, #0x10
- str r3, [r1] @ force reset
- mov r0, r0
+_loop_forever:
- b _loop_forever
+rstctl:
- .word PRM_RSTCTRL
+.globl lowlevel_init +lowlevel_init:
- ldr sp, SRAM_STACK
- str ip, [sp]
- mov ip, lr
- bl s_init @ go setup pll, mux & memory
- ldr ip, [sp]
- mov lr, ip
- mov pc, lr @ back to arch calling code
- @ the literal pools origin
- .ltorg
+SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
diff --git a/arch/arm/cpu/armv7/tegra2/sys_info.c b/arch/arm/cpu/armv7/tegra2/sys_info.c new file mode 100644 index 0000000..6d11dc1 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/sys_info.c @@ -0,0 +1,35 @@ +/*
- (C) Copyright 2010,2011
- NVIDIA Corporation <www.nvidia.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h>
+#ifdef CONFIG_DISPLAY_CPUINFO +/* Print CPU information */ +int print_cpuinfo(void) +{
- puts("TEGRA2\n");
- /* TBD: Add printf of major/minor rev info, stepping, etc. */
- return 0;
+} +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra2/timer.c new file mode 100644 index 0000000..858af0f --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/timer.c @@ -0,0 +1,122 @@ +/*
- (C) Copyright 2010,2011
- NVIDIA Corporation <www.nvidia.com>
- (C) Copyright 2008
- Texas Instruments
- Richard Woodruff r-woodruff2@ti.com
- Syed Moahmmed Khasim khasim@ti.com
- (C) Copyright 2002
- Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- Marius Groeger mgroeger@sysgo.de
- Alex Zuepke azu@sysgo.de
- (C) Copyright 2002
- Gary Jennejohn, DENX Software Engineering, garyj@denx.de
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h>
+DECLARE_GLOBAL_DATA_PTR;
+static timerus_t *timer_base = (timerus_t *)NV_PA_TMRUS_BASE;
+/* counter runs at 1MHz */ +#define TIMER_CLK (1000000) +#define TIMER_LOAD_VAL 0xffffffff
+/* timer without interrupts */ +void reset_timer(void) +{
- reset_timer_masked();
+}
+ulong get_timer(ulong base) +{
- return get_timer_masked() - base;
+}
+void set_timer(ulong t) +{
- gd->tbl = t;
+}
+/* delay x useconds */ +void __udelay(unsigned long usec) +{
- long tmo = usec * (TIMER_CLK / 1000) / 1000;
- unsigned long now, last = readl(&timer_base->cntr_1us);
- while (tmo > 0) {
- now = readl(&timer_base->cntr_1us);
- if (last > now) /* count up timer overflow */
- tmo -= TIMER_LOAD_VAL - last + now;
- else
- tmo -= now - last;
- last = now;
- }
+}
+void reset_timer_masked(void) +{
- /* reset time, capture current incrementer value time */
- gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ);
- gd->tbl = 0; /* start "advancing" time stamp from 0 */
+}
+ulong get_timer_masked(void) +{
- ulong now;
- /* current tick value */
- now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ);
- if (now >= gd->lastinc) /* normal mode (non roll) */
- /* move stamp forward with absolute diff ticks */
- gd->tbl += (now - gd->lastinc);
- else /* we have rollover of incrementer */
- gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
- - gd->lastinc) + now;
- gd->lastinc = now;
- return gd->tbl;
+}
+/*
- This function is derived from PowerPC code (read timebase as long long).
- On ARM it just returns the timer value.
- */
+unsigned long long get_ticks(void) +{
- return get_timer(0);
+}
+/*
- This function is derived from PowerPC code (timebase clock frequency).
- On ARM it returns the number of timer ticks per second.
- */
+ulong get_tbclk(void) +{
- return CONFIG_SYS_HZ;
+} diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h new file mode 100644 index 0000000..52a7269 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -0,0 +1,155 @@ +/*
- (C) Copyright 2010,2011
- NVIDIA Corporation <www.nvidia.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef _CLK_RST_H_ +#define _CLK_RST_H_
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
There are a mixture of lower and upper case hex digits in the comments below - it'd be good to be consistent. And there should be a space before each '*/'. The newline above should be remove too.
Will do. I had changed this once already as per your previous comments, but it must have gotten lost in the V3 patching.
+typedef volatile struct clk_rst_ctlr {
- uint crc_rst_src; /* _RST_SOURCE_0, 0x00*/
- uint crc_rst_dev_l; /* _RST_DEVICES_L_0, 0x04*/
- uint crc_rst_dev_h; /* _RST_DEVICES_H_0, 0x08*/
- uint crc_rst_dev_u; /* _RST_DEVICES_U_0, 0x0C*/
- uint crc_clk_out_enb_l; /* _CLK_OUT_ENB_L_0, 0x10*/
- uint crc_clk_out_enb_h; /* _CLK_OUT_ENB_H_0, 0x14*/
- uint crc_clk_out_enb_u; /* _CLK_OUT_ENB_U_0, 0x18*/
- uint crc_reserved0; /* reserved_0, 0x1c*/
- uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20*/
- uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24*/
- uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28*/
- uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C*/
- uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30*/
- uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34*/
- uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38*/
- uint crc_reserved1; /* reserved_1, 0x3c*/
- uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40*/
- uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44*/
- uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48*/
- uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C*/
- uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50*/
- uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54*/
- uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58*/
- uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C*/
- uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C*/
- uint crc_pllc_base; /* _PLLC_BASE_0, 0x80*/
- uint crc_pllc_out; /* _PLLC_OUT_0, 0x84*/
- uint crc_reserved3; /* reserved_3, 0x88*/
- uint crc_pllc_misc; /* _PLLC_MISC_0, 0x8C*/
- uint crc_pllm_base; /* _PLLM_BASE_0, 0x90*/
- uint crc_pllm_out; /* _PLLM_OUT_0, 0x94*/
- uint crc_reserved4; /* reserved_4, 0x98*/
- uint crc_pllm_misc; /* _PLLM_MISC_0, 0x9C*/
- uint crc_pllp_base; /* _PLLP_BASE_0, 0xA0*/
- uint crc_pllp_outa; /* _PLLP_OUTA_0, 0xA4*/
- uint crc_pllp_outb; /* _PLLP_OUTB_0, 0xA8*/
- uint crc_pllp_misc; /* _PLLP_MISC_0, 0xAC*/
- uint crc_plla_base; /* _PLLA_BASE_0, 0xB0*/
- uint crc_plla_out; /* _PLLA_OUT_0, 0xB4*/
- uint crc_reserved5; /* reserved_5, 0xB8*/
- uint crc_plla_misc; /* _PLLA_MISC_0, 0xBC*/
- uint crc_pllu_base; /* _PLLU_BASE_0, 0xC0*/
- uint crc_reserved6; /* _reserved_6, 0xC4*/
- uint crc_reserved7; /* _reserved_7, 0xC8*/
- uint crc_pllu_misc; /* _PLLU_MISC_0, 0xCC*/
- uint crc_plld_base; /* _PLLD_BASE_0, 0xD0*/
- uint crc_reserved8; /* _reserved_8, 0xD4*/
- uint crc_reserved9; /* _reserved_9, 0xD8*/
- uint crc_plld_misc; /* _PLLD_MISC_0, 0xDC*/
- uint crc_pllx_base; /* _PLLX_BASE_0, 0xE0*/
- uint crc_pllx_misc; /* _PLLX_MISC_0, 0xE4*/
- uint crc_plle_base; /* _PLLE_BASE_0, 0xE8*/
- uint crc_plle_misc; /* _PLLE_MISC_0, 0xEC*/
- uint crc_plls_base; /* _PLLS_BASE_0, 0xF0*/
- uint crc_plls_misc; /* _PLLS_MISC_0, 0xF4*/
- uint crc_reserved10; /* _reserved_10, 0xF8*/
- uint crc_reserved11; /* _reserved_11, 0xFC*/
- uint crc_clk_src_i2s1; /*_I2S1_0, 0x100*/
- uint crc_clk_src_i2s2; /*_I2S2_0, 0x104*/
- uint crc_clk_src_spdif_out; /*_SPDIF_OUT_0, 0x108*/
- uint crc_clk_src_spdif_in; /*_SPDIF_IN_0, 0x10C*/
- uint crc_clk_src_pwm; /*_PWM_0, 0x110*/
- uint crc_clk_src_spi1; /*_SPI1_0, 0x114*/
- uint crc_clk_src_sbc2; /*_SBC2_0, 0x118*/
- uint crc_clk_src_sbc3; /*_SBC3_0, 0x11C*/
- uint crc_clk_src_xio; /*_XIO_0, 0x120*/
- uint crc_clk_src_i2c1; /*_I2C1_0, 0x124*/
- uint crc_clk_src_dvc_i2c; /*_DVC_I2C_0, 0x128*/
- uint crc_clk_src_twc; /*_TWC_0, 0x12C*/
- uint crc_reserved12; /* 0x130*/
- uint crc_clk_src_sbc1; /*_SBC1_0, 0x134*/
- uint crc_clk_src_disp1; /*_DISP1_0, 0x138*/
- uint crc_clk_src_disp2; /*_DISP2_0, 0x13C*/
- uint crc_clk_src_cve; /*_CVE_0, 0x140*/
- uint crc_clk_src_ide; /*_IDE_0, 0x144*/
- uint crc_clk_src_vi; /*_VI_0, 0x148*/
- uint crc_reserved13; /* 0x14C*/
- uint crc_clk_src_sdmmc1; /*_SDMMC1_0, 0x150*/
- uint crc_clk_src_sdmmc2; /*_SDMMC2_0, 0x154*/
- uint crc_clk_src_g3d; /*_G3D_0, 0x158*/
- uint crc_clk_src_g2d; /*_G2D_0, 0x15C*/
- uint crc_clk_src_ndflash; /*_NDFLASH_0, 0x160*/
- uint crc_clk_src_sdmmc4; /*_SDMMC4_0, 0x164*/
- uint crc_clk_src_vfir; /*_VFIR_0, 0x168*/
- uint crc_clk_src_epp; /*_EPP_0, 0x16C*/
- uint crc_clk_src_mp3; /*_MPE_0, 0x170*/
- uint crc_clk_src_mipi; /*_MIPI_0, 0x174*/
- uint crc_clk_src_uarta; /*_UARTA_0, 0x178*/
- uint crc_clk_src_uartb; /*_UARTB_0, 0x17C*/
- uint crc_clk_src_host1x; /*_HOST1X_0, 0x180*/
- uint crc_reserved14; /* 0x184*/
- uint crc_clk_src_tvo; /*_TVO_0, 0x188*/
- uint crc_clk_src_hdmi; /*_HDMI_0, 0x18C*/
- uint crc_reserved15; /* 0x190*/
- uint crc_clk_src_tvdac; /*_TVDAC_0, 0x194*/
- uint crc_clk_src_i2c2; /*_I2C2_0, 0x198*/
- uint crc_clk_src_emc; /*_EMC_0, 0x19C*/
- uint crc_clk_src_uartc; /*_UARTC_0, 0x1A0*/
- uint crc_reserved16; /* 0x1A4*/
- uint crc_clk_src_vi_sensor; /*_VI_SENSOR_0, 0x1A8*/
- uint crc_reserved17; /* 0x1AC*/
- uint crc_reserved18; /* 0x1B0*/
- uint crc_clk_src_sbc4; /*_SBC4_0, 0x1B4*/
- uint crc_clk_src_i2c3; /*_I2C3_0, 0x1B8*/
- uint crc_clk_src_sdmmc3; /*_SDMMC3_0, 0x1BC*/
- uint crc_clk_src_uartd; /*_UARTD_0, 0x1C0*/
- uint crc_clk_src_uarte; /*_UARTE_0, 0x1C4*/
- uint crc_clk_src_vde; /*_VDE_0, 0x1C8*/
- uint crc_clk_src_owr; /*_OWR_0, 0x1CC*/
- uint crc_clk_src_nor; /*_NOR_0, 0x1D0*/
- uint crc_clk_src_csite; /*_CSITE_0, 0x1D4*/
- uint crc_reserved19[9]; /* 0x1D8-1F8*/
- uint crc_clk_src_osc; /*_OSC_0, 0x1FC*/
+} clk_rst_ctlr;
+#endif /* CLK_RST_H */
<snip>
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c new file mode 100644 index 0000000..876facb --- /dev/null +++ b/board/nvidia/common/board.c @@ -0,0 +1,249 @@ +/*
- (C) Copyright 2010,2011
- NVIDIA Corporation <www.nvidia.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/sys_proto.h> +#include "board.h"
+DECLARE_GLOBAL_DATA_PTR;
+const tegra2_sysinfo sysinfo = {
- CONFIG_TEGRA2_BOARD_STRING
+};
+/*
- Routine: board_init
- Description: Early hardware init.
- */
+int board_init(void) +{
- /* boot param addr */
- gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
- /* board id for Linux */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
- return 0;
+}
+/*
- Routine: timer_init
- Description: init the timestamp and lastinc value
- */
+int timer_init(void) +{
- reset_timer();
- return 0;
+}
+/*
- Routine: uart_clock_init
- Description: init the PLL and clock for the UART in uart_num
- */
+void uart_clock_init(int uart_num) +{
Are all these uart functions board-specific? They look more CPU-specific. If that's the case they should be moved somewhere in arch/arm/*. Other boards that use the Tegra2 don't want to duplicate this code or link into Nvidia's board/nvidia directory.
It's Tegra2 SoC-specific - that's not the CPU, per se. I guess I could move it to arch/arm/cpu/armv7/tegra2, if you think it's important enough.
- clk_rst_ctlr *const clkrst = (clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- static int pllp_init_done;
- u32 reg;
- if (!pllp_init_done) {
Remove newline above.
OK.
- /* Override pllp setup for 216MHz operation. */
- reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
- reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
- writel(reg, clkrst->crc_pllp_base);
- reg |= PLL_ENABLE;
- writel(reg, clkrst->crc_pllp_base);
- reg &= ~PLL_BYPASS;
- writel(reg, clkrst->crc_pllp_base);
- pllp_init_done++;
- }
- /* Now do the UART reset/clock enable based on uart_num */
+#if CONFIG_TEGRA2_ENABLE_UARTA
- if (uart_num == UART_A) {
- /* Assert Reset to UART */
- reg = readl(clkrst->crc_rst_dev_l);
- reg |= SWR_UARTA_RST; /* SWR_UARTA_RST = 1 */
- writel(reg, clkrst->crc_rst_dev_l);
- /* Enable clk to UART */
- reg = readl(clkrst->crc_clk_out_enb_l);
- reg |= CLK_ENB_UARTA; /* CLK_ENB_UARTA = 1 */
- writel(reg, clkrst->crc_clk_out_enb_l);
- /* Enable pllp_out0 to UART */
- reg = readl(clkrst->crc_clk_src_uarta);
- reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
- writel(reg, clkrst->crc_clk_src_uarta);
- /* wait for 2us */
- udelay(2);
- /* De-assert reset to UART */
- reg = readl(clkrst->crc_rst_dev_l);
- reg &= ~SWR_UARTA_RST; /* SWR_UARTA_RST = 0 */
- writel(reg, clkrst->crc_rst_dev_l);
- }
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ +#if CONFIG_TEGRA2_ENABLE_UARTD
- if (uart_num == UART_D) {
- /* Assert Reset to UART */
- reg = readl(clkrst->crc_rst_dev_u);
- reg |= SWR_UARTD_RST; /* SWR_UARTD_RST = 1 */
- writel(reg, clkrst->crc_rst_dev_u);
- /* Enable clk to UART */
- reg = readl(clkrst->crc_clk_out_enb_u);
- reg |= CLK_ENB_UARTD; /* CLK_ENB_UARTD = 1 */
- writel(reg, clkrst->crc_clk_out_enb_u);
- /* Enable pllp_out0 to UART */
- reg = readl(clkrst->crc_clk_src_uartd);
- reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
- writel(reg, clkrst->crc_clk_src_uartd);
- /* wait for 2us */
- udelay(2);
- /* De-assert reset to UART */
- reg = readl(clkrst->crc_rst_dev_u);
- reg &= ~SWR_UARTD_RST; /* SWR_UARTD_RST = 0 */
- writel(reg, clkrst->crc_rst_dev_u);
- }
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ +}
+/*
- Routine: pin_mux_uart
- Description: setup the pin muxes/tristate values for UART based on uart_num
- */
+void pin_mux_uart(int uart_num) +{
- pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 reg;
+#if CONFIG_TEGRA2_ENABLE_UARTA
- if (uart_num == UART_A) {
- reg = readl(pmt->pmt_ctl_c);
- reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
- writel(reg, pmt->pmt_ctl_c);
- reg = readl(pmt->pmt_tri_a);
- reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */
- reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */
- writel(reg, pmt->pmt_tri_a);
- }
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ +#if CONFIG_TEGRA2_ENABLE_UARTD
- if (uart_num == UART_D) {
- reg = readl(pmt->pmt_ctl_b);
- reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
- writel(reg, pmt->pmt_ctl_b);
- reg = readl(pmt->pmt_tri_a);
- reg &= ~Z_GMC; /* Z_GMC = normal (0) */
- writel(reg, pmt->pmt_tri_a);
- }
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ +}
+void setup_uart(uart_ctlr *u) +{
- u32 reg;
- /* Prepare the divisor value */
- reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
- /* Set up UART parameters */
- writel(UART_LCR_DLAB, u->uart_lcr);
- writel(reg, u->uart_thr_dlab_0);
- writel(0, u->uart_ier_dlab_0);
- writel(0, u->uart_lcr); /* clear DLAB */
- writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
- UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), u->uart_iir_fcr);
- writel(0, u->uart_ier_dlab_0);
- writel(UART_LCR_WLS_8, u->uart_lcr); /* 8N1 */
- writel(UART_MCR_RTS, u->uart_mcr);
- writel(0, u->uart_msr);
- writel(0, u->uart_spr);
- writel(0, u->uart_irda_csr);
- writel(0, u->uart_asr);
- writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), u->uart_iir_fcr);
- /* Flush any old characters out of the RX FIFO */
- reg = readl(u->uart_lsr);
- while (reg & UART_LSR_DR) {
- reg = readl(u->uart_thr_dlab_0);
- reg = readl(u->uart_lsr);
- }
+}
+/*
- Routine: init_uart
- Description: init the UART clocks, muxes, and baudrate/parity/etc.
- */
+void init_uart(int uart_num) +{ +#if CONFIG_TEGRA2_ENABLE_UARTA
- if (uart_num == UART_A) {
- uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
- uart_clock_init(UART_A);
- /* Enable UARTA - uses config 0 */
- pin_mux_uart(UART_A);
- setup_uart(uart);
- }
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ +#if CONFIG_TEGRA2_ENABLE_UARTD
- if (uart_num == UART_D) {
- uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
- uart_clock_init(UART_D);
- /* Enable UARTD - uses config 0 */
- pin_mux_uart(UART_D);
- setup_uart(uart);
- }
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ +}
+void uart_init(void) +{ +#if (CONFIG_TEGRA2_ENABLE_UARTA)
- init_uart(UART_A);
+#endif +#if (CONFIG_TEGRA2_ENABLE_UARTD)
- init_uart(UART_D);
+#endif +} diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h new file mode 100644 index 0000000..d49e978 --- /dev/null +++ b/board/nvidia/common/board.h @@ -0,0 +1,57 @@ +/*
- (C) Copyright 2010,2011
- NVIDIA Corporation <www.nvidia.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef _COMMON_BOARD_H_ +#define _COMMON_BOARD_H_
+#include <asm/arch/clk_rst.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/uart.h>
+#define NVRM_PLLP_FIXED_FREQ_KHZ 216000 +#define NV_DEFAULT_DEBUG_BAUD 115200
+#define PLL_BYPASS (1 << 31) +#define PLL_ENABLE (1 << 30) +#define PLL_BASE_OVRRIDE (1 << 28) +#define PLL_DIVP (1 << 20) /* post divider, b22:20 */ +#define PLL_DIVM 0x0C /* input divider, b4:0 */
+#define SWR_UARTD_RST (1 << 2) +#define CLK_ENB_UARTD (1 << 2) +#define SWR_UARTA_RST (1 << 6) +#define CLK_ENB_UARTA (1 << 6)
+#define Z_GMC (1 << 29) +#define Z_IRRX (1 << 20) +#define Z_IRTX (1 << 19)
+enum {
- UART_A = 1,
- UART_B,
- UART_C,
- UART_D,
- UART_E
+};
+#endif /* _COMMON_BOARD_H_ */
Same comment about this header. It looks CPU-specific? If so, it should be moved to somewhere in arch/arm.
If /nvidia/common/board.c moves, then I'll move this one, too.
Lastly, its generally good to CC people that have commented on your previous patches (eg Wolfgang and myself) as they are likely to provide more feedback and CC-ing them directly helps to ensure your re-submission doesn't get lost in their inboxes. I promise those are my last comments:)
I've added Wolfgang and Sandeep to the CC list. I'll try to keep it updated.
Best, Peter
Thanks for all the feedback,
Tom