Re: [PATCH] rockchip: Add delay after link-training

On Tue, Jun 2, 2020 at 2:00 AM Kurt Miller kurt@intricatesoftware.com wrote:

On at least the RockPro64, many cards will trip a synchronous abort when first accessing PCIe config space during bus scanning. A delay after link training allows some of these cards to function.

Can you check does the SoC has external PCIe pwr-pin GPIO?

I did see unstable SSD behavior on rock960 but fixed with this. https://github.com/radxa/u-boot/blob/stable-4.4-rockpi4/board/rockchip/evb_r...