[U-Boot] [PATCH 08/14] clk: rockchip: Add SCLK_MAC_SRC clock rate setup

The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested by the integrated phy usuage.

Signed-off-by: David Wu david.wu@rock-chips.com ---

drivers/clk/rockchip/clk_rk322x.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4022065..7276c4a 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -390,6 +390,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC_SRC: case SCLK_MAC: new_rate = rk322x_mac_set_clk(priv->cru, rate); break;