Hi everyone,
This series adds support for the new R40 SoC. The R40 is marketed as the successor to the A20. It is mostly pin compatible (in software) with the A20. It has a somewhat similar memory layout, a hybrid of A20 and newer sun6i gen.. Like the A20, it does not have a PRCM block.
This series makes checkpatch throw out a lot of errors, mostly "no spaces at the start of a line" or "space prohibited after that open parenthesis '('", but fixing them does not improve the readability of the code.
Patch 1 introduces the R40 to U-boot, by adding a Kconfig symbol, fixing up any SoC depends on in Kconfig to disable unsupported features, and reworking board level pinmuxes.
Patch 2 enables using the AXP221s PMIC in I2C mode. The R40 is paired with this PMIC, but it does not have a P2WI controller.
Patch 3 fixes the watchdog reset function for R40. The R40's watchdog register layout is like the A10/A20.
Patch 4 adds mmc pinmux settings for R40.
Patch 5 fixes the PLL lock settings for the R40. The R40's CCU has a new mode for PLL lock, which can be configured and also switched back to the old mode. Here we just use the old mode, which is the same as the other sun6i gen. SoCs.
Patch 6 provides some default DRAM settings for the R40. These were taken from the Bananapi M2 Ultra, the only R40 board available.
Patch 7 adds the compatible string for the R40 PIO. It is mostly compatible with the A20, with a few functions gone, and a few new ones.
Patch 8 adds DRAM initialization support for the R40. The DRAM controller is very similar to the A64 and H5, however the A15 line and CSC1 line are muxed on the same pin. Also the PIR_QSGATE bit must not be set, or DRAM init fails.
Patch 9 enables SPL for R40.
Patch 10 fixes the address of the CPUCFG block on the R40. It is the same as on the A20.
Patch 11 adds a PSCI implementation for the R40. As the register layout is slightly erratic, we just use a macro for the ones that can't fit into the cpucfg register definition structure.
Patch 12 adds a board dts and defconfig for the Bananapi M2 Ultra.
Please have a look.
Regards ChenYu
Chen-Yu Tsai (12): sunxi: Add initial support for R40 sunxi: Enable AXP221s in I2C mode with the R40 SoC sunxi: Fix watchdog reset function for R40 sunxi: Add mmc[1-3] pinmux settings for R40 sunxi: Set PLL lock enable bits for R40 sunxi: Provide defaults for R40 DRAM settings gpio: sunxi: Add compatible string for R40 PIO sunxi: Use H3/A64 DRAM initialization code for R40 sunxi: Enable SPL for R40 sunxi: Fix CPUCFG address for R40 sunxi: Add PSCI support for R40 sunxi: Add support for Bananapi M2 Ultra
arch/arm/cpu/armv7/sunxi/psci.c | 35 ++++- arch/arm/dts/Makefile | 2 + arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 69 +++++++++ arch/arm/dts/sun8i-r40.dtsi | 183 ++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 + arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 +- arch/arm/include/asm/arch-sunxi/dram.h | 4 +- arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 20 ++- arch/arm/include/asm/arch-sunxi/timer.h | 5 +- arch/arm/include/asm/arch-sunxi/watchdog.h | 5 +- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/board.c | 15 +- arch/arm/mach-sunxi/clock_sun6i.c | 9 +- arch/arm/mach-sunxi/cpu_info.c | 2 + arch/arm/mach-sunxi/dram_sun8i_h3.c | 121 ++++++++++++++-- arch/arm/mach-sunxi/pmic_bus.c | 7 + board/sunxi/Kconfig | 18 ++- board/sunxi/MAINTAINERS | 6 + board/sunxi/board.c | 36 ++++- configs/Bananapi_M2_Ultra_defconfig | 15 ++ drivers/gpio/sunxi_gpio.c | 1 + drivers/power/Kconfig | 16 ++- 23 files changed, 530 insertions(+), 49 deletions(-) create mode 100644 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/dts/sun8i-r40.dtsi create mode 100644 configs/Bananapi_M2_Ultra_defconfig