30 May
2017
30 May
'17
10:20 p.m.
On Sun, Apr 30, 2017 at 2:57 PM, Daniel Schwierzeck daniel.schwierzeck@gmail.com wrote:
From: Paul Burton paul.burton@imgtec.com
On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is present. When there is no IOCU we need to writeback or invalidate the data caches at appropriate points. Perform this cache maintenance in the pch_gbe driver which is used on the MIPS Boston development board.
Signed-off-by: Paul Burton paul.burton@imgtec.com Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com
Acked-by: Joe Hershberger joe.hershberger@ni.com