Hi Edward,
On 11/08/2013 02:36 AM, Edward Lin wrote:
In order to be able to support several CPU types in one binary, a duplicate set of pad configuration macros are introduced.
The idea is that a board file should be able to define:
#define MX6_SET_PAD(p, q) \ if (is_cpu_type(MXC_CPU_MX6Q)) \ imx_iomux_v3_setup_pad(MX6Q_##p | q); \ else \ imx_iomux_v3_setup_pad(MX6DL_##p | q);
and then use
MX6_SET_PAD(PAD_CSI0_DAT10__UART1_TXD, MUX_PAD_CTRL(UART_PAD_CTRL)); MX6_SET_PAD(PAD_CSI0_DAT11__UART1_RXD, MUX_PAD_CTRL(UART_PAD_CTRL));
for a readable setup of pad configurations.
The most common case of this will be multiple pads.
These are currently configured in various places as blocks of pads by functional group (i.e. ENET pads, UART pads).
This path doesn't lead us to a single declaration of such lists.
Signed-off-by: Edward Lin edward.lin@technexion.com Signed-off-by: Richard Hu richard.hu@technexion.com
arch/arm/include/asm/arch-mx6/mx6qdl_pins.h | 3290 +++++++++++++++++++++++++++ 1 file changed, 3290 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx6/mx6qdl_pins.h
diff --git a/arch/arm/include/asm/arch-mx6/mx6qdl_pins.h b/arch/arm/include/asm/arch-mx6/mx6qdl_pins.h new file mode 100644 index 0000000..b41a877 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6qdl_pins.h @@ -0,0 +1,3290 @@ +/*
- Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights
Reserved.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ASM_ARCH_MX6_MX6QDL_PINS_H__ +#define __ASM_ARCH_MX6_MX6QDL_PINS_H__
+#include <asm/imx-common/iomux-v3.h>
+enum {
MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0360,0x004C, 0, 0x0000, 0, 0),
...
If we want a single binary to support 6DQ and 6DLS (and I do), we really shouldn't duplicate everything here.
As much as I dislike macro-fu, the enums in mx6q_pins.h and mx6dl_pins.h need to be macros instead of direct declarations of enum constants.
I'll try to write up some notes tomorrow so we can hash through the specifics.
Regards,
Eric