On Tue, Apr 27, 2021 at 12:49 PM Stefan Roese sr@denx.de wrote:
As was discussed on the list, PHY_INTERFACE_MODE_SGMII_2500 is used incorrectly in the Marvell mvpp2 network driver and the Marvell PHY code. This patch removes the references to this macro in the mvpp2 network driver for now.
The correct support shall be implemented at a later time.
Signed-off-by: Stefan Roese sr@denx.de Cc: Konstantin Porotchkin kostap@marvell.com Cc: Stefan Chulski stefanc@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Marek Behun marek.behun@nic.cz
This patch is targeted on-top of the latest Marvell SERDES, mvpp2 and PHY patches to resolve the ongoing discussion of the incorrect usage of SGMII_2500 for now.
drivers/net/mvpp2.c | 53 --------------------------------------------- 1 file changed, 53 deletions(-)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 4c0a7b0a9f5c..b0287f561e2e 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2873,7 +2873,6 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
switch (port->phy_interface) { case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500: val |= MVPP2_GMAC_INBAND_AN_MASK; break; case PHY_INTERFACE_MODE_1000BASEX:@@ -2941,7 +2940,6 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port) val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 || port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) val |= MVPP2_GMAC_PCS_LB_EN_MASK;@@ -3029,48 +3027,6 @@ static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) return 0; }
-static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) -{
u32 val, thresh;/** Configure minimal level of the Tx FIFO before the lower part* starts to read a packet*/thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);/* Disable bypass of sync module */val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;/* configure DP clock select according to mode */val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;/* configure QSGMII bypass according to mode */val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);/** Configure GIG MAC to SGMII mode connected to a fiber* transceiver*/val &= ~MVPP2_GMAC_PORT_TYPE_MASK;writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);/* configure AN 0x9268 */val = MVPP2_GMAC_EN_PCS_AN |MVPP2_GMAC_AN_BYPASS_EN |MVPP2_GMAC_CONFIG_MII_SPEED |MVPP2_GMAC_CONFIG_GMII_SPEED |MVPP2_GMAC_FC_ADV_EN |MVPP2_GMAC_CONFIG_FULL_DUPLEX |MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);-}
static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) { u32 val, thresh; @@ -3241,9 +3197,6 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) case PHY_INTERFACE_MODE_SGMII: gop_gmac_sgmii_cfg(port); break;
case PHY_INTERFACE_MODE_SGMII_2500:gop_gmac_sgmii2_5_cfg(port);break; case PHY_INTERFACE_MODE_1000BASEX: gop_gmac_1000basex_cfg(port); break;@@ -3424,7 +3377,6 @@ static int gop_port_init(struct mvpp2_port *port) break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: /* configure PCS */@@ -3484,7 +3436,6 @@ static void gop_port_enable(struct mvpp2_port *port, int enable) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: if (enable)@@ -3521,7 +3472,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
if (gop_id == 2) { if (phy_type == PHY_INTERFACE_MODE_SGMII ||
phy_type == PHY_INTERFACE_MODE_SGMII_2500 || phy_type == PHY_INTERFACE_MODE_1000BASEX || phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC2_SGMII;@@ -3532,7 +3482,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
if (gop_id == 3) { if (phy_type == PHY_INTERFACE_MODE_SGMII ||
phy_type == PHY_INTERFACE_MODE_SGMII_2500 || phy_type == PHY_INTERFACE_MODE_1000BASEX || phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC3_SGMII;@@ -4531,7 +4480,6 @@ static void mvpp2_start_dev(struct mvpp2_port *port) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: mvpp2_gmac_max_rx_size_set(port);@@ -5270,7 +5218,6 @@ static int mvpp2_start(struct udevice *dev) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: mvpp2_port_power_up(port);-- 2.31.1
Reviewed-by: Ramon Fried rfried.dev@gmail.com