29 Apr
2011
29 Apr
'11
2:47 p.m.
On Apr 22, 2011, at 8:34 AM, Kumar Gala wrote:
From: Timur Tabi timur@freescale.com
Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols.
Signed-off-by: Timur Tabi timur@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 51 ++++++++++++++++-------- arch/powerpc/include/asm/immap_85xx.h | 1 + 2 files changed, 35 insertions(+), 17 deletions(-)
applied to 85xx
- k