[U-Boot] [PATCH v3 14/16] spi: zynq_spi: Add config reg shift named macros

Update the numerical values for baudrate and chipselect with config reg shift named macro's

Signed-off-by: Jagan Teki jteki@openedev.com --- drivers/spi/zynq_spi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index b9cf335..817728c 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -28,6 +28,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */

+#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ +#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ +#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ + #define ZYNQ_SPI_FIFO_DEPTH 128 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ @@ -139,7 +143,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs) * xx01 - cs1 * x011 - cs2 */ - cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK; + cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; writel(cr, &regs->cr); }

@@ -256,14 +260,14 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed) /* Set baudrate x8, if the freq is 0 */ baud_rate_val = 0x2; } else if (plat->speed_hz != speed) { - while ((baud_rate_val < 8) && + while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) && ((plat->frequency / (2 << baud_rate_val)) > speed)) baud_rate_val++; plat->speed_hz = speed / (2 << baud_rate_val); } confr &= ~ZYNQ_SPI_CR_BRD_MASK; - confr |= (baud_rate_val << 3); + confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);

writel(confr, &regs->cr); priv->freq = speed;