Dear Mikhail Zaturenskiy,
In message 97dd5fd20908251235ic0e64eela7c75fb138143dc4@mail.gmail.com you wrote:
static uint sdram_table[] = { /* Single read (offset 0x00 in UPM RAM) */ 0x0F03C004, 0x0FFFC004, 0x00FCC004, 0x0FFFC000, 0x0FF30004, 0x0FFFC004, 0xFFFFC005, 0xFFFFC005, /* Burst read (offset 0x08 in UPM RAM) */ 0x0F03C004, 0x0FFFC004, 0x00FCC004, 0x00FFC000, 0x00FFC000, 0x00FFC000, 0x00FFC000, 0x00FFC000, 0x00FFC000, 0x00FFC000, 0x0FF30000, 0x0FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, /* Single write (offset 0x18 in UPM RAM) */ 0x0F03C004, 0x0FFFC004, 0x00FC0004, 0x0FFFC002, 0x0FF30004, 0X0FFFC004, 0xFFFFC005, 0xFFFFC005, /* Burst write (offset 0x20 in UPM RAM) */ 0x0F03C004, 0x0FFFC004, 0x00FC0004, 0X00FFC000, 0x00FFC000, 0x00FFC000, 0x00FFC000, 0X00FFC000, 0x00FFC000, 0x00FFC000, 0x0FF30002, 0x0FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, /* Refresh (offset 0x30 in UPM RAM) */ 0x0FF0C004, 0x0FFFC004, 0x0FFFC004, 0x0FFFC004, 0xFFFFC005, 0x0FA30004, 0x0FFFC004, 0x0FF0C084, 0x0FFFC004, 0x0FFFC004, 0x0FFFC004, 0x0FFFC084, /* Exception (offset 0x3C in UPM RAM) */ 0x0FFFC004, 0x0FF00004, 0x0FFFC004, 0xFFFFC005 };
Nice formatting.
And the following is my ram init function:
phys_size_t initdram (int board_type) { long int msize; volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); /* Configure SDRAM refresh */ memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */ memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */ udelay(100); /* Run MRS pattern from location 0x35 */ // MZ - was 0x36 memctl->memc_mar = 0x46; // MZ - was 0x88 memctl->memc_mcr = 0x80002235; // MZ - was 0x80002236 udelay(100); memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; // memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM | OR_BI; // MZ - temp, burst inhibit memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_16 | BR_MS_UPMA | BR_V; msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); memctl->memc_or1 |= ~(msize - 1); return msize; }
That's even better. Do you suppose anybody will bother to read any code after you formatted it like this?
Note that this is the U-Boot mailing list, not the submission of entries for the IOCCC.
Also attached is a spreadsheet which illustrates the RAM timing.
Is there something wrong with my RAM table? Am I missing any flags? Something else wrong?
For one, your style of formatting and posting is terribly wrong.
Please see http://www.catb.org/~esr/faqs/smart-questions.html
Best regards,
Wolfgang Denk