The MIPS Malta board has a SOFTRES register. Writing a magic value into that register initiates a board reset.
Use this feature to implement reset support.
Signed-off-by: Gabor Juhos juhosg@openwrt.org Cc: Daniel Schwierzeck daniel.schwierzeck@googlemail.com --- arch/mips/include/asm/malta.h | 3 +++ board/qemu-malta/qemu-malta.c | 11 +++++++++++ 2 files changed, 14 insertions(+)
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index b215164..f2bbf0f 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -13,4 +13,7 @@
#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8)
+#define MALTA_RESET_BASE 0x1f000500 +#define GORESET 0x42 + #endif /* _MIPS_ASM_MALTA_H */ diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c index 9ba711d..9333242 100644 --- a/board/qemu-malta/qemu-malta.c +++ b/board/qemu-malta/qemu-malta.c @@ -8,6 +8,9 @@
#include <common.h>
+#include <asm/io.h> +#include <asm/malta.h> + phys_size_t initdram(int board_type) { return CONFIG_SYS_MEM_SIZE; @@ -18,3 +21,11 @@ int checkboard(void) puts("Board: MIPS Malta CoreLV (Qemu)\n"); return 0; } + +void _machine_restart(void) +{ + void __iomem *reset_base; + + reset_base = (void __iomem *) CKSEG1ADDR(MALTA_RESET_BASE); + __raw_writel(le32_to_cpu(GORESET), reset_base); +}