But the config file for afeb9260 sets it to a value of 89999598, and I can't change that as I don't know that board, but it's near enough to 100000000 to accept that. And I noticed that only because I had the check there in the first place, so it didn't compile with MAKEALL when I only checked for the exact value of 100000000.
That's a very obscure reasoning, me thinks. We don't understand the 89999598, so we accept 85000000...115000000 ? That's true vodoo programming.
I can explain this stuff about master clock :)
1. AT91SAM9260 CPU is run from PLLA on this board. PLLA runs at 180MHz there as maximum stable speed (Actually there are boards with smaller value, I have revisions for 166 and 133MHz here and I want to provide a few patches about this stuff). But 180 MHz is not exact value and it is from 18429952 by multiplication and division. And we need to use it as close as possible because ALL peripherals, except USB depend on this value for timings. Also, a problem is that not all combinations and divisions actually work, and that is hardware feature, too. That's because it is not possible to get this 100MHz value, it is just it - you can't get 100MHz by division of 180MHz by any integer value starting from 2.
I don't see any real reason to pretend we have always 100MHz on this CPU. That might harm a lot. And you can't even imagine how nasty this hardware can be.