This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used.
Thanks to Grant Erickson for all his basic work on this 405EX early bootup.
Signed-off-by: Stefan Roese sr@denx.de --- board/amcc/kilauea/Makefile | 3 +- board/amcc/kilauea/init.S | 167 -------------------------------- board/amcc/kilauea/memory.c | 84 ---------------- cpu/ppc4xx/44x_spd_ddr2.c | 11 ++ include/configs/kilauea.h | 8 +- nand_spl/board/amcc/kilauea/Makefile | 21 ++-- nand_spl/board/amcc/kilauea/config.mk | 5 +- nand_spl/board/amcc/kilauea/u-boot.lds | 1 - 8 files changed, 29 insertions(+), 271 deletions(-) delete mode 100644 board/amcc/kilauea/init.S delete mode 100644 board/amcc/kilauea/memory.c
diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile index 39328c2..981ef3a 100644 --- a/board/amcc/kilauea/Makefile +++ b/board/amcc/kilauea/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cmd_pll.o memory.o -SOBJS = init.o +COBJS = $(BOARD).o cmd_pll.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S deleted file mode 100644 index bf47d6b..0000000 --- a/board/amcc/kilauea/init.S +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson gerickson@nuovations.com - * - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Originally based on code provided from UDTech and AMCC - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; - -#if defined(CONFIG_DDR_ECC) - .extern ecc_init -#endif /* defined(CONFIG_DDR_ECC) */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: -#if !defined(CFG_INIT_DCACHE_CS) -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - - /* - * DDR2 SDRAM Controller Setup - */ - - /* Set Memory Bank Configuration Registers */ - mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); - mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); - mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); - mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); - - /* Set Memory Clock Timing Register */ - mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); - - /* Set Refresh Time Register */ - mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR); - - /* Set SDRAM Timing Registers */ - mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); - mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); - mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); - - /* Set Mode and Extended Mode Registers */ - mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE); - mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); - - /* Set Memory Controller Options 1 Register */ - mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); - - /* Set Manual Initialization Control Registers */ - mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); - mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); - mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); - mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); - mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); - mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); - mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); - mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); - mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); - mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); - mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); - mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); - mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); - mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); - mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); - mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); - - /* Set On-Die Termination Registers */ - mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT); - mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0); - mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1); - - /* Set Write Timing Register */ - mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); - - /* - * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and - * SDRAM0_MCOPT2[IPTR] = 1 - */ - mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \ - SDRAM_MCOPT2_IPTR_EXECUTE); - - /* - * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the - * completion of initialization. - * - * do { - * mfsdram(SDRAM_MCSTAT, val); - * } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); - */ - li r4,SDRAM_MCSTAT - lis r2,SDRAM_MCSTAT_MIC_COMP@h - ori r2,r2,SDRAM_MCSTAT_MIC_COMP@l -0: mtdcr memcfga,r4 - mfdcr r3,memcfgd - clrrwi r3,r3,31 - cmpw cr7,r3,r2 - bne+ cr7,0b - - /* Set Delay Control Registers */ - mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR); - mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC); - mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC); - mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC); - - /* - * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: - * - * mcopt2 = mfsdram(SDRAM_MCOPT2); - */ - li r4,SDRAM_MCOPT2 - mtdcr memcfga,r4 - mfdcr r3,memcfgd - - /* - * mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE); - */ - mtdcr memcfga,r4 - oris r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h - ori r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l - mtdcr memcfgd,r3 - -#if defined(CONFIG_DDR_ECC) - /* - * ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); - */ - mflr r13 - lis r3,CFG_SDRAM_BASE@h - ori r3,r3,CFG_SDRAM_BASE@l - lis r4,(CFG_MBYTES_SDRAM << 20)@h - ori r4,r4,(CFG_MBYTES_SDRAM << 20)@l - bl ecc_init - mtlr r13 -#endif /* defined(CONFIG_DDR_ECC) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -#endif /* !defined(CFG_INIT_DCACHE_CS) */ - - blr diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c deleted file mode 100644 index b7e2344..0000000 --- a/board/amcc/kilauea/memory.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson gerickson@nuovations.com - * - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <i2c.h> - -void sdram_init(void) -{ - return; -} - -#if defined(CONFIG_NAND_U_BOOT) -long int initdram(int board_type) -{ - return (CFG_MBYTES_SDRAM << 20); -} -#endif /* defined(CONFIG_NAND_U_BOOT) */ - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - printf ("testdram\n"); -#if defined (CONFIG_NAND_U_BOOT) - return 0; -#endif - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x00001000; - uint *p; - - for (p = pstart; p < pend; p++) { - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } - - for (p = pstart; p < pend; p++) { - *p = 0x55555555; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test passed!!!\n"); -#endif - return 0; -} -#endif diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index aa4a530..5214918 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -3083,6 +3083,16 @@ static void ppc440sp_sdram_register_dump(void) *---------------------------------------------------------------------------*/ long initdram(int board_type) { + /* + * Only run this SDRAM init code once. For NAND booting + * targets like Kilauea, we call initdram() early from the + * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). + * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) + * which calls initdram() again. This time the controller + * mustn't be reconfigured again since we're already running + * from SDRAM. + */ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) unsigned long val;
/* Set Memory Bank Configuration Registers */ @@ -3178,6 +3188,7 @@ long initdram(int board_type) #if defined(CONFIG_DDR_ECC) ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); #endif /* defined(CONFIG_DDR_ECC) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CFG_MBYTES_SDRAM << 20); } diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 035a40e..205577f 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -170,9 +170,9 @@ * This NAND U-Boot (NUB) is a special U-Boot version which can be started * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 + * On 405EX the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from location 0xfffff000...0xffffffff the + * NAND controller cannot be accessed since it is attached to CS0 too. */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ @@ -511,7 +511,7 @@
/* Memory Bank 2 (FPGA) initialization */ #define CFG_EBC_PB2AP 0x9400C800 -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000)
#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 84bd298..a0293ee 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -29,8 +29,8 @@ LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL
-SOBJS = start.o init.o resetvec.o cache.o -COBJS = memory.o nand_boot.o nand_ecc.o ndfc.o +SOBJS = start.o resetvec.o cache.o +COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -57,10 +57,18 @@ $(nandobj)u-boot-spl: $(OBJS) # create symbolic links for common files
# from cpu directory +$(obj)44x_spd_ddr2.c: ecc.h + @rm -f $(obj)44x_spd_ddr2.c + ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c + $(obj)cache.S: @rm -f $(obj)cache.S ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
+$(obj)ecc.h: + @rm -f $(obj)ecc.h + ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h + $(obj)ndfc.c: @rm -f $(obj)ndfc.c ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c @@ -73,15 +81,6 @@ $(obj)start.S: @rm -f $(obj)start.S ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
-# from board directory -$(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/kilauea/init.S $(obj)init.S - -$(obj)memory.c: - @rm -f $(obj)memory.c - ln -s $(SRCTREE)/board/amcc/kilauea/memory.c $(obj)memory.c - # from nand_spl directory $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk index 2249091..d89ed3f 100644 --- a/nand_spl/board/amcc/kilauea/config.mk +++ b/nand_spl/board/amcc/kilauea/config.mk @@ -29,8 +29,9 @@ # # On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, # in the last 4kBytes of memory space in cache. -# We will copy this SPL into instruction-cache in start.S. So we set -# TEXT_BASE to starting address in i-cache here. +# We will copy this SPL into SDRAM since we can't access the NAND +# controller at CS0 while running from this location. So we set +# TEXT_BASE to starting address in SDRAM here. # TEXT_BASE = 0x00800000
diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds index 084db08..03e0b79 100644 --- a/nand_spl/board/amcc/kilauea/u-boot.lds +++ b/nand_spl/board/amcc/kilauea/u-boot.lds @@ -32,7 +32,6 @@ SECTIONS .text : { start.o (.text) - init.o (.text) nand_boot.o (.text) ndfc.o (.text)