I just ran into this problem also and posted to the list (but got no responses).
After a couple days of sorting through the cfi_flash.c, I noticed that the CFG_FLASH_BANKS_LIST seemed to be the pertinent #define. You need to set this to an address that is beyond the region of flash in which you have stored your u-boot and environment variables. Otherwise, the first thing that the CFI code does is erase it!
Take the following example:
#define CFG_FLASH_PROTECTION 1 /* Real (hardware) sectors protection */ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_CFI #define CFG_FLASH_CFI_DRIVER #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_ENV_IS_IN_FLASH
#ifdef CFG_ENV_IS_IN_FLASH #define CFG_ENV_SECT_SIZE (64 * 1024) /* Reserve 64 kB for env */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_PROTECTED_SIZE (CFG_MONITOR_LEN + CFG_ENV_SECT_SIZE) #define CFG_FLASH_BANKS_LIST { (CFG_FLASH_BASE + CFG_PROTECTED_SIZE) } #endif /* CFG_ENV_IS_IN_FLASH */
What I've done is added CFG_PROTECTED_SIZE as just an intermediate parameter (it will probably go away). It represents the space reserved for U-Boot (256K) + the space reserved for ENV (64K). Just use this as an offset to the CFG_FLASH_BASE and assign that to CFG_FLASH_BANKS_LIST (and it is only that element since you only have one flash bank).
I'm not sure whether you want CFG_FLASH_PROTECTION or not in your environment (I'm pretty sure it doesn't have an effect on the problem you've encountered).
Hope this helps. If anyone sees a flaw in this approach, please let me know!
Scott
----- Original Message ---- From: Miroslaw Dach miroslaw.dach@psi.ch To: u-boot-users@lists.sourceforge.net Sent: Friday, September 7, 2007 8:43:38 AM Subject: [U-Boot-Users] Intel Flash CFI initialisation failure
Dear All,
I am having the problem with Intel Flash TE28F640 J3C120 on my avnet evaluation board (xilinx based with Virtex-4). I have compiled successfully u-boot-1.2.0 and it run well without FLASH support. Eventually I want to store u-boot in Flash but when I compile u-boot with Flash support the u-boot fails during Flash initialization.
My Flash memory is: type: TE28F640 J3C120 (http://www.datasheets.org.uk/datasheet.php?article=3266188) vendor: Intel spec: NOR FLASH 64 Blocks 64 Mbits x8/x16
To support Flash memory I have configured u-boot with the following settings:
#define CFG_FLASH_BASE 0xFF800000 #define CFG_MAX_FLASH_BANKS 1 #define CFG_MAX_FLASH_SECT 64 #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1
The u-boot was compiled successfully but when I booted it I have got the error messages when it came to the Flash initialization:
U-Boot 1.2.0 (Sep 6 2007 - 17:56:34)
### No HW ID - assuming ML403 DRAM: 32 MB Top of RAM usable for U-Boot at: 02000000 Reserving 138k for U-Boot at: 01fdd000 Reserving 129k for malloc() at: 01fbcc00 Reserving 120 Bytes for Board Info at: 01fbcb88 Reserving 48 Bytes for Global Data at: 01fbcb58 Stack Pointer at: 01fbcb38 New Stack Pointer is: 01fbcb38 Now running in RAM - U-Boot at: 01fdd000 FLASH: flash detect cfi fwc addr ff800000 cmd 0 0 8bit x 8 bit fwc addr ff800055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr ff800010 is= 0 51 fwc addr ff800555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr ff800010 is= 0 51 fwc addr ff800000 cmd 0 0000 16bit x 8 bit fwc addr ff8000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff800020 is= 0051 5151 fwc addr ff800aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff800020 is= 0051 5151 fwc addr ff800000 cmd 0 0000 16bit x 16 bit fwc addr ff8000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr ff800020 is= 0051 0051 is= cmd 52(R) addr ff800022 is= 0052 0052 is= cmd 59(Y) addr ff800024 is= 0059 0059 ushort addr is at ff800050 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 device interface is 2 found port 2 chip 2 port 16 bits chip 16 bits ushort addr is at ff800026 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x1 addr[2] = 0x0 addr[3] = 0x0 retval = 0x1 fwc addr ff800000 cmd ff 00ff 16bit x 16 bit fwc addr ff800000 cmd 90 0090 16bit x 16 bit fwc addr ff800000 cmd ff 00ff 16bit x 16 bit fwc addr ff8000aa cmd 98 0098 16bit x 16 bit ushort addr is at ff80002a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x31 addr[2] = 0x0 addr[3] = 0x0 retval = 0x31 ff800020 : 00 51 00 52 00 59 00 01 00 00 00 31 00 00 00 00 .Q.R.Y.....1.... ff800030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 08 .......'.6...... ff800040 : 00 08 00 0b 00 00 00 02 00 02 00 03 00 00 00 17 ................ ff800050 : 00 02 00 00 00 05 00 00 00 01 00 3f 00 00 00 00 ...........?.... ff800060 : 00 02 00 50 00 52 00 49 00 31 00 31 00 ce 00 00 ...P.R.I.1.1.... ff800070 : 00 00 00 00 00 01 00 01 00 00 00 33 00 00 00 01 ...........3.... ff800080 : 00 80 00 00 00 03 00 03 00 03 00 00 00 00 00 00 ................ ff800090 : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ manufacturer is 1 manufacturer id is 0x89 device id is 0x17 device id2 is 0x0 cfi version is 0x3131 size_ratio 1 port 16 bits chip 16 bits found 1 erase regions long addr is at ff80005a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x3f addr[2] = 0x0 addr[3] = 0x0 addr[4] = 0x0 addr[5] = 0x0 addr[6] = 0x0 addr[7] = 0x2 erase_region_count = 64 erase_region_size = 131072 Bus Fault @ 0x01fe4424, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 01fbc978 Data parity signal NIP: 01FE4424 XER: 20000000 LR: 01FE43D8 REGS: 01fbc978 TRAP: 0200 DAR: 00000000MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00
GPR00: 00000000 01FBCA68 C01FC950 01FFF8D0 00000001 01FBCA70 00000001 00000006 GPR08: 00000000 FFC00004 01FBCA73 00000003 01FBC860 30000000 02001600 00000000 GPR16: 00020000 00000001 0000002D 00000000 00000020 00000040 0000002D FFC20000 GPR24: 01FFF950 00000001 00000020 00000004 01FFF8D0 01FBCB58 02001A94 FFC00000 Call backtrace: machine check NIP: FFFFFFFC XER: 00000000 LR: 01FED864 REGS: 01fbc868 TRAP: 0700 DAR: 00000001MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00
Does anybody have an idea what could be wrong?
Best Regards
Mirek
============================================================================= Miroslaw Dach (Miroslaw.Dach@psi.ch) - SLS/Controls Group PSI - Paul Scherrer Institut CH-5232 Villigen =============================================================================
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