When ACPI is enabled over FDT the APs cannot be brought out of reset by the OS using the "FDT spin-table" mechanism, as no FDT is provided to the OS. The APs must be released out of reset in u-boot and then brought up in an ACPI compliant fashion.
When ARMV8_MULTIENTRY is specified the APs are released from reset and will enter U-Boot after it has been relocated as well.
By default ARMV8_MULTIENTRY is not selected, keeping existing behaviour.
TEST: All APs enter U-Boot when run on qemu-system-aarch64 and on real hardware.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Cc: Matthias Brugger mbrugger@suse.com Cc: Peter Robinson pbrobinson@gmail.com Cc: Tom Rini trini@konsulko.com --- Changelog v2: - Drop CPU code from board - Add CPU driver to release APs from reset --- arch/arm/Kconfig | 1 + arch/arm/mach-bcm283x/Kconfig | 2 + arch/arm/mach-bcm283x/init.c | 8 ++ drivers/cpu/Makefile | 1 + drivers/cpu/bcm283x_cpu.c | 194 ++++++++++++++++++++++++++++++++++ 5 files changed, 206 insertions(+) create mode 100644 drivers/cpu/bcm283x_cpu.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 588e293bf2..17cd3d44b6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -644,6 +644,7 @@ config ARCH_ORION5X
config ARCH_BCM283X bool "Broadcom BCM283X family" + select CPU select DM select DM_GPIO select DM_SERIAL diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index b3287ce8bc..de783aa8f5 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -12,6 +12,7 @@ config BCM2836 config BCM2837 bool "Broadcom BCM2837 SoC support" depends on ARCH_BCM283X + select ARCH_EARLY_INIT_R
config BCM2837_32B bool "Broadcom BCM2837 SoC 32-bit support" @@ -29,6 +30,7 @@ config BCM2837_64B config BCM2711 bool "Broadcom BCM2711 SoC support" depends on ARCH_BCM283X + select ARCH_EARLY_INIT_R
config BCM2711_32B bool "Broadcom BCM2711 SoC 32-bit support" diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 7a1de22e0a..e6946c6e94 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -9,6 +9,7 @@ #include <cpu_func.h> #include <init.h> #include <dm/device.h> +#include <dm/uclass.h> #include <fdt_support.h> #include <asm/global_data.h>
@@ -199,7 +200,14 @@ int mach_cpu_init(void) "brcm,bcm2712-pm"); if (offset > soc) rpi_wdog_base = fdt_get_base_address(gd->fdt_blob, offset); + return 0; +} + +int arch_early_init_r(void) +{ + struct udevice *dev;
+ uclass_first_device(UCLASS_CPU, &dev); return 0; }
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index 773395693a..5230408cc0 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
+obj-$(CONFIG_ARCH_BCM283X) += bcm283x_cpu.o obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o obj-$(CONFIG_ARCH_AT91) += at91_cpu.o diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c new file mode 100644 index 0000000000..11dd3008cc --- /dev/null +++ b/drivers/cpu/bcm283x_cpu.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 9elements GmbH + */ + +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/global_data.h> +#include <asm/system.h> +#include <asm/armv8/cpu.h> +#include <asm-generic/sections.h> +#include <cpu.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdt_support.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int cpu_bcm_get_desc(const struct udevice *dev, char *buf, int size) +{ + struct cpu_plat *plat = dev_get_parent_plat(dev); + const char *name; + int ret; + + if (size < 32) + return -ENOSPC; + + if (device_is_compatible(dev, "arm,cortex-a53")) + name = "A53"; + else if (device_is_compatible(dev, "arm,cortex-a72")) + name = "A72"; + else + name = "?"; + + ret = snprintf(buf, size, "Broadcom Cortex-%s at %u MHz", + name, plat->timebase_freq); + + snprintf(buf + ret, size - ret, "\n"); + + return 0; +} + +static int cpu_bcm_get_info(const struct udevice *dev, struct cpu_info *info) +{ + struct cpu_plat *plat = dev_get_parent_plat(dev); + + info->cpu_freq = plat->timebase_freq * 1000; + info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU); + return 0; +} + +static int cpu_bcm_get_count(const struct udevice *dev) +{ + ofnode node; + int num = 0; + + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; + + if (!ofnode_is_enabled(node)) + continue; + + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; + + if (!strcmp(device_type, "cpu")) + num++; + } + + return num; +} + +static int cpu_bcm_get_vendor(const struct udevice *dev, char *buf, int size) +{ + snprintf(buf, size, "Broadcom"); + return 0; +} + +#ifdef CONFIG_ARM64 +static int cpu_bcm_is_current(struct udevice *dev) +{ + struct cpu_plat *plat = dev_get_parent_plat(dev); + + if (plat->cpu_id == (read_mpidr() & 0xffff)) + return 1; + + return 0; +} +#endif + +static int bcm_cpu_on(struct udevice *dev) +{ + ofnode node = dev_ofnode(dev); + uintptr_t *start_address; + u64 release_addr64; + const char *prop; + + if (!ofnode_is_enabled(node)) + return 0; + + prop = ofnode_read_string(node, "enable-method"); + if (!prop || strcmp(prop, "spin-table")) + return 1; + + release_addr64 = ofnode_read_u64_default(node, "cpu-release-addr", ~0ULL); + if (release_addr64 == ~0ULL) + return 1; + + start_address = map_physmem(release_addr64, sizeof(uintptr_t), MAP_NOCACHE); + + /* Point to U-Boot start */ + *start_address = (uintptr_t)_start; + flush_dcache_all(); + + /* Send an event to wake up the secondary CPU. */ + asm("dsb ishst\n" + "sev"); + udelay(10000); + + unmap_physmem(start_address, MAP_NOCACHE); + return 0; +} + +static int bcm_init(struct udevice *dev) +{ + int ret = 0; + + /* The armstub holds the secondary CPUs in a spinloop. When + * ARMV8_MULTIENTRY is enabled release the secondary CPUs and + * let them enter U-Boot as well. + */ + if (CONFIG_IS_ENABLED(ARMV8_MULTIENTRY)) + ret = bcm_cpu_on(dev); + return ret; +} + +static const struct cpu_ops cpu_bcm_ops = { + .get_desc = cpu_bcm_get_desc, + .get_info = cpu_bcm_get_info, + .get_count = cpu_bcm_get_count, + .get_vendor = cpu_bcm_get_vendor, +#ifdef CONFIG_ARM64 + .is_current = cpu_bcm_is_current, +#endif +}; + +static const struct udevice_id cpu_bcm_ids[] = { + { .compatible = "arm,cortex-a53" }, /* RPi 3 */ + { .compatible = "arm,cortex-a72" }, /* RPi 4 */ + { } +}; + +static int cpu_bcm_bind(struct udevice *dev) +{ + struct cpu_plat *plat = dev_get_parent_plat(dev); + + plat->cpu_id = dev_read_addr(dev); + + return bcm_init(dev); +} + +static int bcm_cpu_probe(struct udevice *dev) +{ + struct cpu_plat *plat = dev_get_parent_plat(dev); + struct clk clk; + int ret; + + /* Get a clock if it exists */ + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) { + ret = clk_enable(&clk); + if (ret && (ret != -ENOSYS || ret != -EOPNOTSUPP)) + return ret; + ret = clk_get_rate(&clk); + if (!IS_ERR_VALUE(ret)) + plat->timebase_freq = ret; + } + + return ret; +} + +U_BOOT_DRIVER(cpu_bcm_drv) = { + .name = "bcm283x_cpu", + .id = UCLASS_CPU, + .of_match = cpu_bcm_ids, + .ops = &cpu_bcm_ops, + .probe = bcm_cpu_probe, + .bind = cpu_bcm_bind, + .flags = 0, +};