Hi,
On 13 January 2016 at 16:24, Simon Glass sjg@chromium.org wrote:
This series provides a number of new features and improvements leading to enabling the keyboard (via Chrome OS EC) on jerry. This is conneected via SPI and uses its own message protocol.
Features and fixes are needed in the rockchip code to make this work include: - RK808 PMIC and regulator driver - Fixes and improvements to the i2c and SPI drivers - A full implementation of the GPIO driver - Additional clock support - Additional pinctrl support
The series moves a few rockchip boards to use the full pinctrl driver. I'm not sure this is a great idea, as it slows down start-up noticeably. It is currently needed for the display series (to come), but I intend to change that.
Simon Glass (50): dm: clk: Add support for decoding clocks from the device tree dm: core: Don't set pinctrl for pinctrl devices dm: pinctrl: Add a function to parse PIN_CONFIG flags dm: pmic: Add 'reg status' to show all regulators dts: Bring in pinctrl device tree binding power: Add base support for the RK808 PMIC power: Add support for RK808 regulators dm: Add a power sequencing uclass rockchip: Avoid using MMC code when not booting from MMC rockchip: Convert the PMU IOMUX registers into an array rockchip: mmc: Use a pwrseq device if available rockchip: Correct the defconfig order rockchip: Use pwrseq for MMC start-up on jerry rockchip: jerry: Disable pmic-int-1 setup to avoid a hang rockchip: Use a separate clock ID for clocks rockchip: clock: Rename the general clock variable to gclk_rate rockchip: clk: Add a function to get a peripheral clock rate rockchip: clock: Add a function to find a clock by ID rockchip: i2c: Update the driver to use the new clock ID rockchip: spi: Update the driver to use the new clock ID rockchip: spi: Avoid setting the pinctrl twice rockchip: mmc: Update the driver to use the new clock ID rockchip: pinctrl: Add a full pinctrl driver rockchip: Move firefly and jerry to use the full pinctrl rockchip: jerry: Enable the RK808 PMIC and regulator rockchip: Disable simple-bus in SPL for firefly-rk3288, jerry rockchip: jerry: Drop unused options gpio: Allow 's' as an abbreviation for 'status' cros_ec: Disable the Chrome OS EC in SPL dm: i2c: Allow muxes to be enabled for SPL separately spi: Correct device tree usage in spi_flash_decode_fdt() dm: power: Allow regulators to be omitted from SPL dm: pinctrl: Add a way for a GPIO driver to obtain a pin function dm: core: Export uclass_find_device_by_of_offset() dm: power: Tidy up debugging output and return values dm: power: Allow regulators to not implement all operations dm: clk: Add a simple version of clk_get_by_index() rockchip: sdram: Use the rk_clr/setreg() interface rockchip: reset: Use the rk_clr/setreg() interface rockchip: spi: Remember the last speed to avoid re-setting it rockchip: spi: Correct the bus init code rockchip: clk: Make rkclk_get_clk() SoC-specific rockchip: pinctrl: Reduce the size for SPL rockchip: pinctrl: Implement the get_gpio_mux() method rockchip: gpio: Read the GPIO value correctly rockchip: gpio: Implement the get_function() method rockchip: spi: Implement the delays rockchip: spi: Correct chip-enable code rockchip: spi: Remove the explicit pinctrl setting rockchip: jerry: Enable the Chrome OS EC
I know this is pretty soon, but I'd like to apply this to u-boot-rockchip in the next day or two. If there are any more comments, please send them through.
Regards, Simon