Implement UART clocks for all Allwinner SoC clock drivers via clock map descriptor table.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a10.c | 9 +++++++++ drivers/clk/sunxi/clk_a10s.c | 5 +++++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 7 +++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 5 +++++ drivers/clk/sunxi/clk_r40.c | 9 +++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++++ 9 files changed, 57 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index ee499c402a..d145d37217 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = { [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, [CLK_AHB_SPI3] = { 0x060, BIT(23), NULL },
+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_APB1_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_APB1_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_APB1_UART6] = { 0x06c, BIT(22), NULL }, + [CLK_APB1_UART7] = { 0x06c, BIT(23), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index 0c71e5b698..d2e9af2555 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL }, + #ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 06a2e6bc79..9dbc83c531 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = { [CLK_BUS_EHCI] = { 0x060, BIT(26), NULL }, [CLK_BUS_OHCI] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + #ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a5c6628c63..40803a1d64 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = { [CLK_AHB1_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_AHB1_OHCI2] = { 0x060, BIT(31), NULL },
+ [CLK_APB2_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB2_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB2_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB2_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_APB2_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_APB2_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index e991c8d2d1..ae96ce7803 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = { [CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL }, [CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 47b7672e7f..5c1235fa7b 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = { [CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL }, [CLK_BUS_OHCI0] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 1cc32a0b91..3be6f4cdac 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_OHCI2] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI3] = { 0x060, BIT(31), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 24c26ad3be..1e5b1d10f7 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = { [CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_BUS_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_BUS_UART6] = { 0x06c, BIT(22), NULL }, + [CLK_BUS_UART7] = { 0x06c, BIT(23), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 525b6dcb39..e12ab2bc65 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = { [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(24), NULL },
+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },