Re: [U-Boot] [PATCH] net: fec: Avoid MX28 bus sync issue

12 Jul 2013


      On Thu, Jul 11, 2013 at 8:03 PM, Marek Vasut marex@denx.de wrote:
...
The MX28 multi-layer AHB bus can be too slow and trigger the
FEC DMA too early, before all the data hit the DRAM. This patch
ensures the data are written in the RAM before the DMA starts.
Please see the comment in the patch for full details.
This patch was produced with an amazing help from Albert Aribaud,
who pointed out it can possibly be such a bus synchronisation
issue.
Signed-off-by: Marek Vasut marex@denx.de
Cc: Albert ARIBAUD albert.u.boot@aribaud.net
Cc: Fabio Estevam fabio.estevam@freescale.com
Cc: Stefano Babic sbabic@denx.de
Excellent, managed to transfer 90MB via TFTP on mx28evk without a
single timeout.
Tested-by: Fabio Estevam fabio.estevam@freescale.com