
16 Jan
2017
16 Jan
'17
8:44 a.m.
On Fri, Jan 13, 2017 at 08:28:07AM +0000, André Przywara wrote:
On 13/01/17 08:09, Vishnu Patekar wrote: Hi Vishnu,
Even for the single core cortex-a7, SMP bit should be set before enabling MMU and cache.
Reference: Cortex A7 r0p5 TRM. section 4.3.31.
Ah, good point, thanks for the heads up. I was misled by the SMP name when answering Icenowy. So it's about coherency in general and we need the bit for TLBs and caches to work as well. Let me check what that means for the other SoCs and whether we need to rename the config symbol then.
If we still needs it, x86 has a CONFIG_SMP symbol, that would be better to just leverage that.
Thanks! Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com