Re: [U-Boot] [PATCH] Add support s3c2440 NAND controller

2012/4/19 Ilya Averyanov averyanovin@gmail.com

arch/arm/include/asm/arch-s3c24x0/s3c2410.h | 4 +- arch/arm/include/asm/arch-s3c24x0/s3c2440.h | 4 +- arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 13 +- drivers/mtd/nand/Makefile | 3 +- drivers/mtd/nand/s3c2410_nand.c | 189 ------------------- drivers/mtd/nand/s3c24x0_nand.c | 268 +++++++++++++++++++++++++++ 6 files changed, 283 insertions(+), 198 deletions(-) delete mode 100644 drivers/mtd/nand/s3c2410_nand.c create mode 100644 drivers/mtd/nand/s3c24x0_nand.c

diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h index 4fbdf20..71eb33e 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h @@ -99,9 +99,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; }

-static inline struct s3c2410_nand *s3c2410_get_base_nand(void) +static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) {

• return (struct s3c2410_nand *)S3C2410_NAND_BASE;

• return (struct s3c24x0_nand *)S3C2410_NAND_BASE;

}

static inline struct s3c24x0_uart diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h index 8c606e3..8b9a5b0 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -97,9 +97,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; }

-static inline struct s3c2440_nand *s3c2440_get_base_nand(void) +static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) {

• return (struct s3c2440_nand *)S3C2440_NAND_BASE;

• return (struct s3c24x0_nand *)S3C2440_NAND_BASE;

}

static inline struct s3c24x0_uart diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index ca978c9..d82251d 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -151,20 +151,19 @@ struct s3c24x0_lcd { };

+struct s3c24x0_nand { #ifdef CONFIG_S3C2410 /* NAND FLASH (see S3C2410 manual chapter 6) */ -struct s3c2410_nand { u32 nfconf; u32 nfcmd; u32 nfaddr; u32 nfdata; u32 nfstat; u32 nfecc; -}; #endif #ifdef CONFIG_S3C2440 /* NAND FLASH (see S3C2440 manual chapter 6) */ -struct s3c2440_nand { u32 nfconf; u32 nfcont; u32 nfcmd; @@ -176,8 +175,14 @@ struct s3c2440_nand { u32 nfstat; u32 nfstat0; u32 nfstat1; -};

• u32 nfmecc0;

• u32 nfmecc1;
  

• u32 nfsecc;
  

• u32 nfsblk;
• u32 nfeblk;

#endif +};

/* UART (see manual chapter 11) */ diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 1d1b628..b080cf7 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -58,7 +58,8 @@ COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o COBJS-$(CONFIG_NAND_NDFC) += ndfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o -COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o +COBJS-$(CONFIG_NAND_S3C2410) += s3c24x0_nand.o +COBJS-$(CONFIG_NAND_S3C2440) += s3c24x0_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c deleted file mode 100644 index e1a459b..0000000 --- a/drivers/mtd/nand/s3c2410_nand.c +++ /dev/null @@ -1,189 +0,0 @@ -/*

• • (C) Copyright 2006 OpenMoko, Inc.
• • Author: Harald Welte laforge@openmoko.org
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h>

-#include <nand.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <asm/io.h>

-#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)

-#define S3C2410_ADDR_NALE 4 -#define S3C2410_ADDR_NCLE 8

-#ifdef CONFIG_NAND_SPL

-/* in the early stage of NAND flash booting, printf() is not available */ -#define printf(fmt, args...)

-static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{

• int i;
• struct nand_chip *this = mtd->priv;
• for (i = 0; i < len; i++)

•    buf[i] = readb(this->IO_ADDR_R);
  

-} -#endif

-static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{

• struct nand_chip *chip = mtd->priv;
• struct s3c2410_nand *nand = s3c2410_get_base_nand();
• debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
• if (ctrl & NAND_CTRL_CHANGE) {

•    ulong IO_ADDR_W = (ulong)nand;
  

•    if (!(ctrl & NAND_CLE))
  

•        IO_ADDR_W |= S3C2410_ADDR_NCLE;
  

•    if (!(ctrl & NAND_ALE))
  

•        IO_ADDR_W |= S3C2410_ADDR_NALE;
  

•    chip->IO_ADDR_W = (void *)IO_ADDR_W;
  

•    if (ctrl & NAND_NCE)
  

•        writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
  

•               &nand->nfconf);
  

•    else
  

•        writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
  

•               &nand->nfconf);
  

• }
• if (cmd != NAND_CMD_NONE)

•    writeb(cmd, chip->IO_ADDR_W);
  

-}

-static int s3c2410_dev_ready(struct mtd_info *mtd) -{

• struct s3c2410_nand *nand = s3c2410_get_base_nand();
• debug("dev_ready\n");
• return readl(&nand->nfstat) & 0x01;

-}

-#ifdef CONFIG_S3C2410_NAND_HWECC -void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) -{

• struct s3c2410_nand *nand = s3c2410_get_base_nand();
• debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
• writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);

-}

-static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,

•                  u_char *ecc_code)
  

-{

• struct s3c2410_nand *nand = s3c2410_get_base_nand();
• ecc_code[0] = readb(&nand->nfecc);
• ecc_code[1] = readb(&nand->nfecc + 1);
• ecc_code[2] = readb(&nand->nfecc + 2);
• debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",

•       mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
  

• return 0;

-}

-static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,

•                 u_char *read_ecc, u_char *calc_ecc)
  

-{

• if (read_ecc[0] == calc_ecc[0] &&

•    read_ecc[1] == calc_ecc[1] &&
  

•    read_ecc[2] == calc_ecc[2])
  

•    return 0;
  

• printf("s3c2410_nand_correct_data: not implemented\n");
• return -1;

-} -#endif

-int board_nand_init(struct nand_chip *nand) -{

• u_int32_t cfg;
• u_int8_t tacls, twrph0, twrph1;
• struct s3c24x0_clock_power *clk_power =

s3c24x0_get_base_clock_power();

• struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
• debug("board_nand_init()\n");
• writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
• /* initialize hardware */

-#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)

• tacls = CONFIG_S3C24XX_TACLS;
• twrph0 = CONFIG_S3C24XX_TWRPH0;
• twrph1 = CONFIG_S3C24XX_TWRPH1;

-#else

• tacls = 4;
• twrph0 = 8;
• twrph1 = 8;

-#endif

• cfg = S3C2410_NFCONF_EN;
• cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
• cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
• cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
• writel(cfg, &nand_reg->nfconf);
• /* initialize nand_chip data structure */
• nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
• nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
• nand->select_chip = NULL;
• /* read_buf and write_buf are default */
• /* read_byte and write_byte are default */

-#ifdef CONFIG_NAND_SPL

• nand->read_buf = nand_read_buf;

-#endif

• /* hwcontrol always must be implemented */
• nand->cmd_ctrl = s3c2410_hwcontrol;
• nand->dev_ready = s3c2410_dev_ready;

-#ifdef CONFIG_S3C2410_NAND_HWECC

• nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
• nand->ecc.calculate = s3c2410_nand_calculate_ecc;
• nand->ecc.correct = s3c2410_nand_correct_data;
• nand->ecc.mode = NAND_ECC_HW;
• nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
• nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;

-#else

• nand->ecc.mode = NAND_ECC_SOFT;

-#endif

-#ifdef CONFIG_S3C2410_NAND_BBT

• nand->options = NAND_USE_FLASH_BBT;

-#else

• nand->options = 0;

-#endif

• debug("end of nand_init\n");
• return 0;

-} diff --git a/drivers/mtd/nand/s3c24x0_nand.c b/drivers/mtd/nand/s3c24x0_nand.c new file mode 100644 index 0000000..67b44ee --- /dev/null +++ b/drivers/mtd/nand/s3c24x0_nand.c @@ -0,0 +1,268 @@ +/*

• • (C) Copyright 2006 OpenMoko, Inc.
• • Author: Harald Welte laforge@openmoko.org
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h>

+#include <nand.h> +#include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h>

+#define S3C2410_NFCONF_EN (1<<15) +#define S3C2410_NFCONF_512BYTE (1<<14) +#define S3C2410_NFCONF_4STEP (1<<13) +#define S3C2410_NFCONF_INITECC (1<<12) +#define S3C2410_NFCONF_nFCE (1<<11) +#define S3C2410_NFCONF_TACLS(x) ((x)<<8) +#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) +#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)

+#define S3C2410_ADDR_NALE 4 +#define S3C2410_ADDR_NCLE 8

+#define S3C2440_NFCONT_INITECC (1<<4) +#define S3C2440_NFCONF_nFCE (1<<1) +#define S3C2440_ADDR_NALE 0x8 +#define S3C2440_ADDR_NCLE 0xC

+#ifdef CONFIG_NAND_SPL

+/* in the early stage of NAND flash booting, printf() is not available */ +#define printf(fmt, args...)

+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{

• int i;
• struct nand_chip *this = mtd->priv;
• for (i = 0; i < len; i++)

•    buf[i] = readb(this->IO_ADDR_R);
  

+} +#endif

+#ifdef CONFIG_S3C2440 +static void s3c2440_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{

• struct nand_chip *chip = mtd->priv;
• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
• if (ctrl & NAND_CTRL_CHANGE) {

•    ulong IO_ADDR_W = (ulong)nand;
  

•    if (!(ctrl & NAND_CLE))
  

•        IO_ADDR_W |= S3C2440_ADDR_NCLE;
  

•    if (!(ctrl & NAND_ALE))
  

•        IO_ADDR_W |= S3C2440_ADDR_NALE;
  

•    chip->IO_ADDR_W = (void *)IO_ADDR_W;
  

•    if (ctrl & NAND_NCE)
  

•        writel(readl(&nand->nfcont) & ~S3C2440_NFCONF_nFCE,
  

•               &nand->nfcont);
  

•    else
  

•        writel(readl(&nand->nfcont) | S3C2440_NFCONF_nFCE,
  

•               &nand->nfcont);
  

• }
• if (cmd != NAND_CMD_NONE)

•    writeb(cmd, chip->IO_ADDR_W);
  

+}

+static int s3c2440_dev_ready(struct mtd_info *mtd) +{

• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• debug("dev_ready\n");
• return readl(&nand->nfstat) & 0x01;

+} +#else +static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{

• struct nand_chip *chip = mtd->priv;
• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
• if (ctrl & NAND_CTRL_CHANGE) {

•    ulong IO_ADDR_W = (ulong)nand;
  

•    if (!(ctrl & NAND_CLE))
  

•        IO_ADDR_W |= S3C2410_ADDR_NCLE;
  

•    if (!(ctrl & NAND_ALE))
  

•        IO_ADDR_W |= S3C2410_ADDR_NALE;
  

•    chip->IO_ADDR_W = (void *)IO_ADDR_W;
  

•    if (ctrl & NAND_NCE)
  

•        writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
  

•               &nand->nfconf);
  

•    else
  

•        writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
  

•               &nand->nfconf);
  

• }
• if (cmd != NAND_CMD_NONE)

•    writeb(cmd, chip->IO_ADDR_W);
  

+}

+static int s3c2410_dev_ready(struct mtd_info *mtd) +{

• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• debug("dev_ready\n");
• return readl(&nand->nfstat) & 0x01;

+} +#endif

+#ifdef CONFIG_SYS_S3C2440_NAND_HWECC +void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{

• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
• writel((readl(&nand->nfcont) & ~(1 << 5)) | S3C2440_NFCONT_INITECC,

&nand->nfcont); +}

+static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,

•                  u_char *ecc_code)
  

+{

• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• unsigned long ecc = readl(&nand->nfmecc0);
• ecc_code[0] = ecc;
• ecc_code[1] = ecc >> 8;
• ecc_code[2] = ecc >> 16;
• debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",

•       mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
  

• return 0;

+}

+#elif defined(CONFIG_SYS_S3C2410_NAND_HWECC) +void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{

• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
• writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);

+}

+static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,

•                  u_char *ecc_code)
  

+{

• struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
• ecc_code[0] = readb(&nand->nfecc);
• ecc_code[1] = readb(&nand->nfecc + 1);
• ecc_code[2] = readb(&nand->nfecc + 2);
• debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",

•       mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
  

• return 0;

+} +#endif

+static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,

•                 u_char *read_ecc, u_char *calc_ecc)
  

+{

• if (read_ecc[0] == calc_ecc[0] &&

•    read_ecc[1] == calc_ecc[1] &&
  

•    read_ecc[2] == calc_ecc[2])
  

•    return 0;
  

• printf("s3c2410_nand_correct_data: not implemented\n");
• return -1;

+}

+int board_nand_init(struct nand_chip *nand) +{

• u_int8_t tacls, twrph0, twrph1;
• struct s3c24x0_clock_power *clk_power =

s3c24x0_get_base_clock_power();

• struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand();
• debug("board_nand_init()\n");
• writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
• /* initialize hardware */

+#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)

• tacls = CONFIG_S3C24XX_TACLS;
• twrph0 = CONFIG_S3C24XX_TWRPH0;
• twrph1 = CONFIG_S3C24XX_TWRPH1;

+#else

• tacls = 4;
• twrph0 = 8;
• twrph1 = 8;

+#endif

+#ifdef CONFIG_S3C2440

• writel(readl(&nand_reg->nfconf) | ((tacls-1)<<12)|((twrph0 -

1)<<8)|((twrph1 - 1)<<4)|(0<<0), &nand_reg->nfconf);

writel((0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0), &nand_reg->nfcont); +#else

• writel(S3C2410_NFCONF_EN|S3C2410_NFCONF_TACLS(tacls -

1)|S3C2410_NFCONF_TWRPH0(twrph0 - 1)|S3C2410_NFCONF_TWRPH1(twrph1 - 1) ,

•        &nand_reg->nfconf);
  

+#endif

• /* initialize nand_chip data structure */
• nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
• nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
• nand->select_chip = NULL;
• /* read_buf and write_buf are default */
• /* read_byte and write_byte are default */

+#ifdef CONFIG_NAND_SPL

• nand->read_buf = nand_read_buf;

+#endif

• /* hwcontrol always must be implemented */

+#ifdef CONFIG_S3C2440

• nand->cmd_ctrl = s3c2440_hwcontrol;
• nand->dev_ready = s3c2440_dev_ready;

+#else

• nand->cmd_ctrl = s3c2410_hwcontrol;
• nand->dev_ready = s3c2410_dev_ready;

+#endif

+#ifdef CONFIG_SYS_S3C2440_NAND_HWECC

• nand->ecc.hwctl = s3c2440_nand_enable_hwecc;
• nand->ecc.calculate = s3c2440_nand_calculate_ecc;
• nand->ecc.correct = s3c24x0_nand_correct_data;
• nand->ecc.mode = NAND_ECC_HW;
• nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
• nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;

+#elif defined(CONFIG_SYS_S3C2410_NAND_HWECC)

• nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
• nand->ecc.calculate = s3c2410_nand_calculate_ecc;
• nand->ecc.correct = s3c24x0_nand_correct_data;
• nand->ecc.mode = NAND_ECC_HW;
• nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
• nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;

+#else

• nand->ecc.mode = NAND_ECC_SOFT;

+#endif

+#ifdef CONFIG_S3C2410_NAND_BBT

• nand->options = NAND_USE_FLASH_BBT;

+#else

• nand->options = 0;

+#endif

• debug("end of nand_init\n");
• return 0;

+}

1.7.7.1.msysgit.0

Can anyone comment?