From: Chin Liang See chin.liang.see@intel.com
Add misc support such as EMAC and cpu info printout for Stratix SoC
Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 76 ++++++++++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 75 ++----------------- arch/arm/mach-socfpga/misc_s10.c | 115 ++++++++++++++++++++++++++++++ 5 files changed, 197 insertions(+), 71 deletions(-) create mode 100644 arch/arm/mach-socfpga/misc_s10.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 910eb6f..b253914 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -32,6 +32,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += misc_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 0b65783..8466023 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -8,6 +8,7 @@ #define _MISC_H_
void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode); +int socfpga_eth_reset(void);
struct bsel { const char *mode; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 00eff90..cee3296 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -20,11 +20,14 @@ #include <asm/arch/nic301.h> #include <asm/arch/scu.h> #include <asm/pl310.h> +#include <asm/arch/sdram.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif
struct bsel bsel_str[] = { { "rsvd", "Reserved", }, @@ -53,6 +56,7 @@ void enable_caches(void) #endif }
+#ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { /* Disable the L2 cache */ @@ -73,6 +77,7 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) @@ -136,3 +141,74 @@ int arch_cpu_init(void)
return 0; } + +#if !defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} +#endif + +#ifdef CONFIG_ETH_DESIGNWARE +int socfpga_eth_reset(void) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; + int nodes[3]; /* Max. 3 GMACs */ + int ret, count; + int i, node; + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || (args.args_count != 1)) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); + } + + return 0; +} +#else +int socfpga_eth_reset(void) +{ + return 0; +}; +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 91ddb79..6149c8a 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -67,77 +67,6 @@ void dwmac_deassert_reset(const unsigned int of_reset_id, /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); } - -static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - -static int socfpga_eth_reset(void) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - /* Put both GMACs into RESET state. */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - dwmac_deassert_reset(args.args[0], phy_modereg); - } - - return 0; -} -#else -static int socfpga_eth_reset(void) -{ - return 0; -}; #endif
static const struct { @@ -222,6 +151,10 @@ int arch_misc_init(void) env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) env_set("fpgatype", socfpga_fpga_model[fpga_id].var); + + /* Put both GMACs into RESET state. */ + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); return socfpga_eth_reset(); } #endif diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c new file mode 100644 index 0000000..cc45dcc --- /dev/null +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/misc.h> +#include <asm/pl310.h> + +#include <dt-bindings/reset/altr,rst-mgr-s10.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + /* Put the emac we're using into reset. + * This is required before configuring the PHY interface + */ + socfpga_emac_manage_reset(of_reset_id, 1); + + clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET), + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); + + socfpga_emac_manage_reset(of_reset_id, 0); +} +#endif + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + puts("CPU: Intel FPGA SoCFPGA Platform\n"); + puts("FPGA: Intel FPGA Stratix 10\n"); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + return socfpga_eth_reset(); +} +#endif + +int arch_early_init_r(void) +{ + return 0; +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); + socfpga_sdram_apply_static_cfg(); + writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[1], &nic301_regs->remap); +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) + socfpga_bridges_reset(1); +#endif + break; + case 'd': /* Disable */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) + writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, &sdr_ctrl->fpgaport_rst); + socfpga_sdram_apply_static_cfg(); + writel(0, &reset_manager_base->brg_mod_reset); + writel(1, &nic301_regs->remap); +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) + socfpga_bridges_reset(0); +#endif + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +);