Make AFEB9260 build again.
Signed-off-by: Sergey Lapin slapin@ossfans.org --- board/afeb9260/afeb9260.c | 103 ++++++++++++++++++++++++------------------- boards.cfg | 2 +- include/configs/afeb9260.h | 27 +++++++++--- 3 files changed, 78 insertions(+), 54 deletions(-)
diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index 3c37557..ac40e2e 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -31,7 +31,7 @@ #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> #include <asm/arch/hardware.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <netdev.h> @@ -48,29 +48,30 @@ DECLARE_GLOBAL_DATA_PTR; static void afeb9260_nand_hw_init(void) { unsigned long csa; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; +
- /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | - AT91_SMC_TDF_(2)); - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); - + writel( AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel( AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel( AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel( AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -81,10 +82,15 @@ static void afeb9260_nand_hw_init(void) #ifdef CONFIG_MACB static void afeb9260_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
- /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
/* * Disable pull-up on: @@ -103,24 +109,22 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | - AT91_RSTC_URSTEN); - - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); - + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); +
/* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | @@ -129,23 +133,28 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer);
at91_macb_hw_init(); } #endif - +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clocks for all PIOs */ + writel( (1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + return 0; +} int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* arch number of AT91SAM9260EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AFEB9260; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND afeb9260_nand_hw_init(); #endif @@ -159,8 +168,10 @@ int board_init(void)
int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; }
@@ -174,7 +185,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01); #endif return rc; } diff --git a/boards.cfg b/boards.cfg index d2cacc8..99f1896 100644 --- a/boards.cfg +++ b/boards.cfg @@ -72,7 +72,7 @@ netstar arm arm925t voiceblue arm arm925t omap1510inn arm arm925t - ti aspenite arm arm926ejs - Marvell armada100 -afeb9260 arm arm926ejs - - at91 +afeb9260 arm arm926ejs - - at91 afeb9260:AT91SAM9260 at91cap9adk arm arm926ejs - atmel at91 snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 36a2a46..02206e0 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -25,12 +25,19 @@
#ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/hardware.h>
-#define CONFIG_AT91_LEGACY +#define CONFIG_SYS_TEXT_BASE 0x21f00000
/* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */ @@ -46,8 +53,14 @@ /* * Hardware drivers */ +#define CONFIG_ATMEL_LEGACY #define CONFIG_AT91_GPIO 1 +#define CONFIG_AT91_PULLUP 1 + + #define CONFIG_ATMEL_USART 1 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 @@ -82,8 +95,8 @@
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI @@ -100,7 +113,7 @@ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) @@ -134,12 +147,13 @@
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x21e00000
#undef CONFIG_SYS_USE_DATAFLASH_CS0 #define CONFIG_SYS_USE_DATAFLASH_CS1 1 #undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
/* bootstrap + u-boot + env + linux in dataflash on CS1 */ #define CONFIG_ENV_IS_IN_DATAFLASH 1 @@ -172,5 +186,4 @@ #ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported #endif - #endif