Hi Stefano,
On 06/17/2014 08:40 AM, Stefano Babic wrote:
Hi Fabio,
On 14/06/2014 22:29, Fabio Estevam wrote:
From: Fabio Estevam fabio.estevam@freescale.com
Add the pin definitions for mx6sx.
A base question. There was a lot of work to try to abstract the pin definitions for the i.MX6 SOCs. For QUAD and DUAL, the pins are defined with the MX6_PAD_DECL macro. It works differently according to the selected CPU. If more as one CPU is supported in the same image, the check is done at runtime.
Previously, we had IOMUX_PAD, I know. Is there any special reason we cannot use MX6_PAD_DECL even for this new SOC ? I will not want to go back ignoring a lot of work that was done to merge the SOCs together.
The rationale for the MX6_PAD_DECL came from the fact that the i.MX6DQ and i.MX6DLS cpu variants had different address schemes, but were pin-compatible.
The i.MX6SL (and i.MX6SX) are not, so any board supporting these processors only supports that processor.
Regards,
Eric